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2020 – today
- 2024
[j25]Shea Smith
, Armin Tajalli, Yen-Cheng Kuan, Shiuh-Hua Wood Chiang:
A Digital Background Calibration Circuit for Coarse-Fine Timing Mismatch in VCO-Based ADCs. IEEE Trans. Circuits Syst. II Express Briefs 71(8): 3650-3654 (2024)- [j24]Behdad Jamadi, Shiuh-Hua Wood Chiang, Armin Tajalli:
Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. 32(7): 1364-1368 (2024) - [c65]Rajath Bindiganavile, Asif Wahid, Armin Tajalli:
A 29 GHz Sub-Sampling PLL with 25.6-fs-rms RJ based on a Discrete-Time Integrating PD in 45nm RF SOI. CICC 2024: 1-2 - [c64]Asif Wahid, Rajath Bindiganavile, Armin Tajalli:
Hadamard Multi-Tone Signaling in Multi-Wire Pulse Amplitude Modulation for Next Generation Wireline Communication. ISCAS 2024: 1-5 - [c63]Armin Tajalli:
Speed-Noise-Power Trade-Offs in Design of Scaled FET Circuits Using $\mathrm{C}/\mathrm{I}_{\mathrm{D}}$ Methodology. LASCAS 2024: 1-5 - [c62]Michael Keyser, Farzad T. Ordubadi, Armin Tajalli:
Effect of Parameter Drift on the Accuracy of Analog CNN Accelerators. MWSCAS 2024: 923-927 - 2023
- [j23]Asif Wahid, Jacob Atkinson, Rajath Bindiganavile, Farzan Jazaeri, Armin Tajalli:
Noise-Aware FET Circuit Design Based on C/ID-Invariant. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2330-2334 (2023) - [c61]Shea Smith, Taylor Barton, Yen-Cheng Kuan, Armin Tajalli, Mau-Chung Frank Chang, Shiuh-Hua Wood Chiang:
A 0.12-V 200-Hz-BW 10-Bit ADC Using Quad-Channel VCO and Interpolation Linearization. A-SSCC 2023: 1-3 - [c60]Alec Adair, Armin Tajalli:
Computational Efficiency of Circuit Design and Optimization Algorithms: A Comparative Study. ISCAS 2023: 1-5 - [c59]Shea Smith, Armin Tajalli, Shiuh-Hua Wood Chiang:
A VCO Linearization Technique Using Dual-VCO and Interpolation for Time-Based ADCs. MWSCAS 2023: 996-1000 - [c58]Behdad Jamadi, Fariborz T. Ordubadi, Armin Tajalli:
Design Flow to Develop Wideband Inverter-Based Circuits Using C/ID Methodology. SMACD 2023: 1-4 - [c57]Sakthidasan Kalidasan, Armin Tajalli:
Extending C/ID Methodology for Optimal Implementation of Single-Stage Discrete-Time Amplifiers. SMACD 2023: 1-4 - 2022
- [j22]Jacob Atkinson, Anthony Bailey, Armin Tajalli:
Systematic Design of Loop Circuit Topologies Using C/IDS Methodology. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1538-1542 (2022) - [c56]Armin Tajalli, Amin Shokrollahi:
Balanced Circuit Topologies and Their Applications in Data Movement. MWSCAS 2022: 1-6 - 2021
- [j21]Armin Tajalli:
Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/IDS Methodology. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 631-640 (2021) - [j20]Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici:
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1132-1140 (2021) - [c55]Asif Wahid, Rajath Bindiganavile, Armin Tajalli:
Optimal PAM Order for Wireline Communication. ISCAS 2021: 1-5 - [c54]Rajath Bindiganavile, Armin Tajalli:
A Controllable KVCO Ring VCO Topology. MWSCAS 2021: 732-736 - 2020
- [j19]Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh:
A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET. IEEE J. Solid State Circuits 55(4): 1108-1123 (2020) - [c53]Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Amit Gupta, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh:
Short-Reach and Pin-Efficient Interfaces Using Correlated NRZ. CICC 2020: 1-8 - [c52]Asif Wahid, Sayed Abdullah Sadat, Mostafa Ardakani, Armin Tajalli:
Power System Emulator Based on PLL Architecture. ISCAS 2020: 1-4 - [c51]Asif Wahid, Armin Tajalli:
Digitally-Assisted Peak Detector for Periodic Signal. MWSCAS 2020: 974-977 - [c50]Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli:
Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector. VLSI-SoC (Selected Papers) 2020: 21-37 - [c49]Amin Aghighi, Massood Tabib-Azar, Armin Tajalli:
An ULP Self-Supplied Brain Interface Circuit. VLSI-SOC 2020: 100-104 - [c48]Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli:
Energy and Area Efficient Mixed-Mode MCMC MIMO Detector. VLSI-SOC 2020: 105-110 - [c47]Amin Aghighi, Armin Tajalli, Mohammad Taherzadeh-Sani:
A Low-Power 10 to 15 Gb/s Common-Gate CTLE Based on Optimized Active Inductors. VLSI-SOC 2020: 171-175
2010 – 2019
- 2019
- [c46]Farzan Jazaeri, Arnout Beckers, Armin Tajalli, Jean-Michel Sallese:
A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics. MIXDES 2019: 15-25 - [c45]Jacob Atkinson, Amin Aghighi, Stuart Anderson, Anthony Bailey, Mitchell Crane, Armin Tajalli:
Multi-Stage Current-Steering Amplifier Design Based on Extended gm/ID Methodology. MWSCAS 2019: 129-132 - [c44]Rajath Bindiganavile, Armin Tajalli:
Spectrum-Efficient Communication Over Copper Using Hybrid Amplitude and Spatial Signaling. MWSCAS 2019: 1061-1064 - [c43]Amin Aghighi, Jacob Atkinson, Nickolas Bybee, Stuart Anderson, Mitchell Crane, Anthony Bailey, Reuben Morell, Ahmed Hassanin, Armin Tajalli:
CMOS Amplifier Design Based on Extended $g_{m}/I_{D}$ Methodology. NEWCAS 2019: 1-4 - [c42]Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici:
ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links. NEWCAS 2019: 1-4 - [c41]Firat Celik, Ayca Akkaya, Armin Tajalli, Andreas Burg, Yusuf Leblebici:
JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS. PRIME 2019: 101-104 - [c40]Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, John Fox, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, G. Paul, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh:
A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET. VLSI Circuits 2019: 92- - 2018
- [c39]Ayca Akkaya, Firat Celik, Armin Tajalli, Yusuf Leblebici:
A 10b SAR ADC with Widely Scalable Sampling Rate and AGC Amplifier Front-End. NORCAS 2018: 1-6 - 2017
- [j18]Gain Kim, Chen Cao, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1387-1391 (2017) - 2016
- [j17]Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects. IEEE J. Solid State Circuits 51(4): 992-1002 (2016) - [j16]Gain Kim, Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 63-II(12): 1126-1130 (2016) - [c38]Kiarash Gharibdoust, Gain Kim, Armin Tajalli, Yusuf Leblebici:
A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces. ISCAS 2016: 2905 - [c37]Amin Shokrollahi, Dario Albino Carnelli, John Fox, Klaas L. Hofstra, Brian Holden, Ali Hormati, Peter Hunt, Margaret Johnston, John Keay, Sergio Pesenti, Richard Simpson, David Stauffer, Andrew Stewart, Giuseppe Surace, Armin Tajalli, Omid Talebi Amiri, Anton Tschank, Roger Ulrich, Christoph Walter, Fabio Licciardello, Yohann Mogentale, Anant Singh:
10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS. ISSCC 2016: 182-183 - [c36]Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS. NEWCAS 2016: 1-4 - 2015
- [j15]Nikola Katic, Ibrahim Kazi, Armin Tajalli, Alexandre Schmid, Yusuf Leblebici:
A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces. Int. J. Circuit Theory Appl. 43(11): 1597-1614 (2015) - [j14]Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces. IEEE J. Solid State Circuits 50(12): 3133-3144 (2015) - [j13]Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Alexandre Schmid, Yusuf Leblebici:
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 458-467 (2015) - [c35]Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Yusuf Leblebici:
Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators. ISCAS 2015: 157-160 - [c34]Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS. ISSCC 2015: 1-3 - [c33]Kiarash Gharibdoust, Armin Tajalli, Yusuf Leblebici:
A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS. VLSIC 2015: 180- - 2014
- [c32]Nikola Katic, Ibrahim Kazi, Armin Tajalli, Alexandre Schmid, Yusuf Leblebici:
A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces. NORCHIP 2014: 1-4 - 2012
- [j12]Armin Tajalli, Yusuf Leblebici:
Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 903-907 (2012) - 2011
- [j11]Armin Tajalli, Yusuf Leblebici:
Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter. IEEE Trans. Circuits Syst. II Express Briefs 58-II(3): 159-163 (2011) - [j10]Armin Tajalli, Yusuf Leblebici:
Design Trade-offs in Ultra-Low-Power Digital Nanoscale CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2189-2200 (2011) - [c31]Armin Tajalli, Yusuf Leblebici:
Design trade-offs in ultra-low-power CMOS and STSCL digital systems. ECCTD 2011: 544-547 - 2010
- [j9]Armin Tajalli, Yusuf Leblebici:
Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits. J. Low Power Electron. 6(1): 211-217 (2010) - [c30]Armin Tajalli, Yusuf Leblebici:
Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. DATE 2010: 711-716 - [c29]Armin Tajalli, Yusuf Leblebici:
Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution. ESSCIRC 2010: 174-177 - [c28]Armin Tajalli, Yusuf Leblebici:
A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems. ESSCIRC 2010: 242-245
2000 – 2009
- 2009
- [j8]Armin Tajalli, Yusuf Leblebici:
A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology. IEEE J. Solid State Circuits 44(2): 538-548 (2009) - [j7]Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici:
Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP. Microelectron. J. 40(6): 973-978 (2009) - [j6]Armin Tajalli, Massimo Alioto, Yusuf Leblebici:
Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits. IEEE Trans. Circuits Syst. II Express Briefs 56-II(2): 127-131 (2009) - [j5]Armin Tajalli, Yusuf Leblebici:
Leakage Current Reduction Using Subthreshold Source-Coupled Logic. IEEE Trans. Circuits Syst. II Express Briefs 56-II(5): 374-378 (2009) - [c27]Armin Tajalli, Yusuf Leblebici:
A widely-tunable and ultra-low-power MOSFET-C filter operating in subthreshold. CICC 2009: 593-596 - [c26]Armin Tajalli, Yusuf Leblebici:
Subthreshold SCL for ultra-low-power SRAM and low-activity-rate digital systems. ESSCIRC 2009: 164-167 - [c25]Armin Tajalli, Yusuf Leblebici:
Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design. ISCAS 2009: 2553-2556 - 2008
- [j4]Pooyan Sakian, Mohsen Saffari, Seyed Mojtaba Atarodi, Armin Tajalli:
Low-power analogue phase interpolator based clock and data recovery with high-frequency tolerance. IET Circuits Devices Syst. 2(5): 409-421 (2008) - [j3]Armin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici, Eric A. Vittoz:
Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications. IEEE J. Solid State Circuits 43(7): 1699-1710 (2008) - [c24]Thomas Liechti, Armin Tajalli, Omer Can Akgun, Zeynep Toprak Deniz, Yusuf Leblebici:
A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology. APCCAS 2008: 21-24 - [c23]Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer:
Improving the power-delay product in SCL circuits using source follower output stage. ISCAS 2008: 145-148 - [c22]Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici:
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. PATMOS 2008: 21-30 - 2007
- [j2]Armin Tajalli, Paul Muller, Yusuf Leblebici:
Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits. J. Low Power Electron. 3(3): 345-354 (2007) - [j1]Armin Tajalli, Paul Muller, Yusuf Leblebici:
A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication. IEEE J. Solid State Circuits 42(10): 2235-2244 (2007) - [c21]Armin Tajalli, Eric A. Vittoz, Yusuf Leblebici, Elizabeth J. Brauer:
Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept. ESSCIRC 2007: 304-307 - [c20]Ramin Zanbaghi, Seyed Mojtaba Atarodi, Armin Tajalli:
A Power Optimized Base-Band Circuitry for the Low-IF Receivers. ISCAS 2007: 1693-1696 - [i1]Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici:
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. CoRR abs/0710.4727 (2007) - 2006
- [c19]Mohsen Moezzi, Ramin Zanbaghi, Mojtaba Atarodi, Armin Tajalli:
A Q-Enhanced Biquadratic Gm-C Filter for High Frequency Applications. ICECS 2006: 248-251 - [c18]Habib Adrang, Reza Lotfi, Khalil Mafinejhad, Armin Tajalli, Saeed Mehrmanesh:
A low-power CMOS Gm-C filter for wireless receiver applications with on-chip automatic tuning system. ISCAS 2006 - [c17]Saeed Saeedi, Saeid Mehrmanesh, Armin Tajalli, Seyed Mojtaba Atarodi:
A technique to suppress tail current flicker noise in CMOS LC VCOs. ISCAS 2006 - [c16]Mohsen Saffari, Seyed Mojtaba Atarodi, Armin Tajalli:
A 1/4 rate linear phase detector for PLL-based CDR circuits. ISCAS 2006 - [c15]Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici:
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. ISCAS 2006 - 2005
- [c14]Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi:
A fractional delay-locked loop for on chip clock generation applications. ASP-DAC 2005: 1300-1309 - [c13]Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici:
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. DATE 2005: 258-263 - [c12]Armin Tajalli, Paul Muller, Mojtaba Atarodi, Yusuf Leblebici:
A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology. ESSCIRC 2005: 193-196 - [c11]Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi:
Analysis of jitter peaking and jitter accumulation in re-circulating delay-locked loops. ISCAS (3) 2005: 2255-2258 - [c10]Pooya Torkzadeh, Armin Tajalli, Seyed Mojtaba Atarodi:
A wide tuning range, 1 GHz-2.5 GHz DLL-based fractional frequency synthesizer. ISCAS (5) 2005: 5031-5034 - [c9]Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici:
A low-power, multichannel gated oscillator-based CDR for short-haul applications. ISLPED 2005: 107-110 - 2004
- [c8]Armin Tajalli, Seyed Mojtaba Atarodi, Abbas Khodaverdi, Farzad Sahandi Esfanjani:
Design and optimization of a high PSRR CMOS bandgap voltage reference. ISCAS (1) 2004: 45-48 - [c7]Armin Tajalli, Saeid Mehrmanesh, Seyed Mojtaba Atarodi:
A duty cycle control circuit for high speed applications. ISCAS (1) 2004: 781-784 - 2003
- [c6]Armin Tajalli, Abbas Khodaverdi, Seyed Mojtaba Atarodi:
A compact, low power, fully integrated clock frequency doubler. ICECS 2003: 563-566 - [c5]Armin Tajalli, Seyed Mojtaba Atarodi:
Structured design of an integrated subscriber line interface system and circuit. ISCAS (2) 2003: 284-287 - [c4]Armin Tajalli, Seyed Mojtaba Atarodi:
A compact biquadratic gm-C filter structure for low-voltage and high frequency applications. ISCAS (1) 2003: 501-504 - [c3]Armin Tajalli, Seyed Mojtaba Atarodi:
Design considerations for a 1.5-V, 10.7-MHz bandpass gm-C filter in a 0.6µm standard CMOS technology. ISCAS (1) 2003: 521-524 - 2002
- [c2]Mohammad B. Vahidfar, Armin Tajalli, Seyed Mojtaba Atarodi:
A low-power subscriber line interface circuit in a high-voltage CMOS technology. ISCAS (5) 2002: 409-412 - 2000
- [c1]Armin Tajalli, Mojtaba Atarodi, Akbar Adibi:
A 1.5-V supply, video range frequency, Gm-C filter. ISCAS 2000: 148-151
Coauthor Index
Seyed Mojtaba Atarodi
aka: Mojtaba Atarodi
aka: Mojtaba Atarodi
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