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ORCIDJosep Llosa
- > Home > Persons > Josep Llosa
Publications
- 2022
[c35]Apan Qasem, Hartwig Anzt, Eduard Ayguadé, Katharine J. Cahill
, Ramon Canal, Jany Chan, Eric Fosler-Lussier, Fritz Göbel, Arpan Jain, Marcel Koch, Mateusz Kuzak, Josep Llosa, Raghu Machiraju, Xavier Martorell, Pratik Nayak, Shameema Oottikkal, Marcin Ostasz, Dhabaleswar K. Panda, Dirk Pleiter, Rajiv Ramnath, Maria-Ribera Sancho, Alessio Sclocco, Aamir Shafi, Hanno Spreeuw, Hari Subramoni, Karen Tomko:
Lightning Talks of EduHPC 2022. EduHPC@SC 2022: 42-49- 2008
- [j14]Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
Power-efficient VLIW design using clustering and widening. Int. J. Embed. Syst. 3(3): 141-149 (2008) - 2004
- [j12]Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
High-performance and low-power VLIW cores for numerical computations. Int. J. High Perform. Comput. Netw. 1(4): 171-179 (2004) - [j10]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. Int. J. Parallel Program. 32(6): 447-474 (2004) - [j7]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Register Constrained Modulo Scheduling. IEEE Trans. Parallel Distributed Syst. 15(5): 417-430 (2004) - [c27]Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units. SAMOS 2004: 88-97 - 2003
- [c25]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Hierarchical Clustered Register File Organization for VLIW Processors. IPDPS 2003: 77 - [c23]Miquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero:
Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. ISHPC 2003: 113-126 - 2001
- [j5]Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt:
Lifetime-Sensitive Modulo Scheduling in a Production Environment. IEEE Trans. Computers 50(3): 234-249 (2001) - [j4]David López, Josep Llosa, Mateo Valero, Eduard Ayguadé:
Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. IEEE Trans. Computers 50(10): 1033-1051 (2001) - [c18]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
MIRS: Modulo Scheduling with Integrated Register Spilling. LCPC 2001: 239-253 - [c17]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Modulo scheduling with integrated register spilling for clustered VLIW architectures. MICRO 2001: 160-169 - 2000
- [c14]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Two-level hierarchical register file organization for VLIW processors. MICRO 2000: 137-146 - [c13]Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Improved spill code generation for software pipelined loops. PLDI 2000: 134-144 - 1999
- [c11]David López, Josep Llosa, Eduard Ayguadé, Mateo Valero:
Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. ICPP 1999: 22-29 - 1998
- [j2]Josep Llosa, Eduard Ayguadé, Mateo Valero:
Quantitative Evaluation of Register Pressure on Software Pipelined Loops. Int. J. Parallel Program. 26(2): 121-142 (1998) - [j1]Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González:
Modulo Scheduling with Reduced Register Pressure. IEEE Trans. Computers 47(6): 625-638 (1998) - [c10]David López, Josep Llosa, Mateo Valero, Eduard Ayguadé:
Resource Widening Versus Replication: Limits and Performance-cost Trade-off. International Conference on Supercomputing 1998: 441-448 - [c8]David López, Josep Llosa, Mateo Valero, Eduard Ayguadé:
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. MICRO 1998: 237-246 - 1997
- [c6]David López, Mateo Valero, Josep Llosa, Eduard Ayguadé:
Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs. International Conference on Supercomputing 1997: 12-19 - 1996
- [c5]Josep Llosa, Antonio González, Eduard Ayguadé, Mateo Valero:
Swing module scheduling: a lifetime-sensitive approach. IEEE PACT 1996: 80-86 - [c4]Josep Llosa, Mateo Valero, Eduard Ayguadé:
Heuristics for Register-Constrained Software Pipelining. MICRO 1996: 250-261 - 1995
- [c3]Josep Llosa, Mateo Valero, Eduard Ayguadé:
Non-Consistent Dual Register Files to Reduce Register Pressure. HPCA 1995: 22-31 - [c2]Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González:
Hypernode reduction modulo scheduling. MICRO 1995: 350-360 - 1994
- [c1]Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé:
Using Sacks to Organize Registers in VLIW Machines. CONPAR 1994: 628-639
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