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ORCIDThomas M. Conte
Tom Conte 0001
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- affiliation: Georgia Institute of Technology, Atlanta GA, USA
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2020 – today
- 2024
[i12]Kenneth Brown, Fred Chong, Kaitlin N. Smith, Tom Conte, Austin Adams, Aniket S. Dalvi, Christopher Kang, Joshua Viszlai:
5 Year Update to the Next Steps in Quantum Computing. CoRR abs/2403.08780 (2024)- [i11]Austin Adams, Sharjeel Khan, Jeffrey S. Young, Thomas M. Conte:
Qwerty: A Basis-Oriented Quantum Programming Language. CoRR abs/2404.12603 (2024) - 2023
- [c66]Akihiro Hayashi, Austin Adams, Jeffrey Young, Alexander J. McCaskey, Eugene F. Dumitrescu, Vivek Sarkar, Thomas M. Conte
:
Enabling Multi-threading in Heterogeneous Quantum-Classical Programming Models. IPDPS Workshops 2023: 509-516 - [c65]John Vincent Atanasoff, Gordon Bell, Kiril L. Boyanov, Charles G. Call, Carl K. Chang, Thomas M. Conte, Vladimir Getov, John L. Gustafson, Hironori Kasahara, Dejan S. Milojicic, Michael R. Williams:
The Invention of Electronic Digital Computing - Plenary Panel Summary. JVA 2023: 8 - [c64]Thomas M. Conte:
Status Update on the IEEE Rebooting Computing Initiative. JVA 2023: 9-13 - [i10]Akihiro Hayashi, Austin Adams, Jeffrey Young, Alexander J. McCaskey, Eugene F. Dumitrescu, Vivek Sarkar, Thomas M. Conte:
Enabling Multi-threading in Heterogeneous Quantum-Classical Programming Models. CoRR abs/2301.11559 (2023) - 2022
- [j46]Bobin Deng, Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook:
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems. IEEE Trans. Computers 71(3): 613-627 (2022) - [c63]Sara Karamati, Clayton Hughes, K. Scott Hemmert, Ryan E. Grant, Whit Schonbein, Scott Levy, Thomas M. Conte, Jeffrey Young, Richard W. Vuduc:
"Smarter" NICs for faster molecular dynamics: a case study. IPDPS 2022: 583-594 - [i9]Sara Karamati, Clayton Hughes, K. Scott Hemmert, Ryan E. Grant, Whit Schonbein, Scott Levy, Thomas M. Conte, Jeffrey Young, Richard W. Vuduc:
"Smarter" NICs for faster molecular dynamics: a case study. CoRR abs/2204.05959 (2022) - 2021
- [j45]Todd Hylton, Thomas M. Conte, Mark D. Hill:
A vision to compute like nature: thermodynamically. Commun. ACM 64(6): 35-38 (2021) - [j44]Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook:
SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads. ACM Trans. Archit. Code Optim. 18(4): 56:1-56:24 (2021) - [c62]Austin Adams, Elton Pinto, Jeffrey Young, Creston D. Herold, Alexander J. McCaskey, Eugene F. Dumitrescu, Thomas M. Conte:
Enabling a Programming Environment for an Experimental Ion Trap Quantum Testbed. ICRC 2021: 14-23 - [i8]Thomas M. Conte, Ian T. Foster, William Gropp, Mark D. Hill:
Advancing Computing's Foundation of US Industry & Society. CoRR abs/2101.01284 (2021) - 2020
- [j43]Sriseshan Srikanth, Anirudh Jain, Joseph M. Lennon, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook:
MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams. ACM Trans. Archit. Code Optim. 16(4): 35:1-35:26 (2020) - [j42]Eric R. Hein, Srinivas Eswar, Abdurrahman Yasar, Jiajia Li, Jeffrey S. Young, Thomas M. Conte, Ümit V. Çatalyürek, Richard W. Vuduc, E. Jason Riedy, Bora Uçar:
Programming Strategies for Irregular Algorithms on the Emu Chick. ACM Trans. Parallel Comput. 7(4): 25:1-25:25 (2020) - [c61]Michael P. Frank, Robert W. Brocato, Thomas M. Conte, Alexander H. Hsia, Anirudh Jain, Nancy A. Missert, Karpur Shukla, Brian D. Tierney:
Special Session: Exploring the Ultimate Limits of Adiabatic Circuits. ICCD 2020: 21-24 - [c60]Tong Zhou, Jun Shirako, Anirudh Jain, Sriseshan Srikanth, Thomas M. Conte, Richard W. Vuduc, Vivek Sarkar:
Intrepydd: performance, productivity, and portability for data science application kernels. Onward! 2020: 65-83 - [i7]Benjamin Zorn, Tom Conte, Keith Marzullo, Suresh Venkatasubramanian:
Evolving Methods for Evaluating and Disseminating Computing Research. CoRR abs/2007.01242 (2020)
2010 – 2019
- 2019
- [j41]Jeffrey S. Young, Eric R. Hein, Srinivas Eswar, Patrick Lavin, Jiajia Li, E. Jason Riedy, Richard W. Vuduc, Tom Conte:
A microbenchmark characterization of the Emu chick. Parallel Comput. 87: 60-69 (2019) - [c59]Jeffrey S. Young, E. Jason Riedy, Thomas M. Conte, Vivek Sarkar, Prasanth Chatarasi, Sriseshan Srikanth:
Experimental Insights from the Rogues Gallery. ICRC 2019: 80-87 - [c58]Vladimir Getov, Peter M. Kogge, Thomas M. Conte:
Application Performance of Physical System Simulations. PARCO 2019: 251-260 - [c57]Will Powell, E. Jason Riedy, Jeffrey S. Young, Thomas M. Conte:
Wrangling Rogues: A Case Study on Managing Experimental Post-Moore Architectures. PEARC 2019: 61 - [i6]Eric R. Hein, Srinivas Eswar, Abdurrahman Yasar, Jiajia Li, Jeffrey S. Young, Thomas M. Conte, Ümit V. Çatalyürek, Rich Vuduc, E. Jason Riedy, Bora Uçar:
Programming Strategies for Irregular Algorithms on the Emu Chick. CoRR abs/1901.02775 (2019) - [i5]Tom Conte, Erik DeBenedictis, Natesh Ganesh, Todd Hylton, John Paul Strachan, R. Stanley Williams, Alexander A. Alemi, Lee Altenberg, Gavin E. Crooks, James P. Crutchfield, Lídia del Rio, Josh Deutsch, Michael Robert DeWeese, Khari Douglas, Massimiliano Esposito, Michael P. Frank, Robert Fry, Peter Harsha, Mark D. Hill, Christopher T. Kello, Jeff Krichmar, Suhas Kumar, Shih-Chii Liu, Seth Lloyd, Matteo Marsili, Ilya Nemenman, Alex Nugent, Norman H. Packard, Dana Randall, Peter Sadowski, Narayana Santhanam, Robert Shaw, Adam Z. Stieg, Elan Stopnitzky, Christof Teuscher, Chris Watkins, David H. Wolpert, J. Joshua Yang, Yan Yufik:
Thermodynamic Computing. CoRR abs/1911.01968 (2019) - 2018
- [j40]Thomas M. Conte, Erik P. DeBenedictis, Avi Mendelson, Dejan S. Milojicic:
Rebooting Computers to Avoid Meltdown and Spectre. Computer 51(4): 74-77 (2018) - [j39]F. D. Wright, Thomas M. Conte:
Standards: Roadmapping Computer Technology Trends Enlightens Industry. Computer 51(6): 100-103 (2018) - [j38]Onur Mutlu, Scott A. Mahlke, Thomas M. Conte, Wen-Mei W. Hwu:
Iterative Modulo Scheduling. IEEE Micro 38(1): 115-117 (2018) - [j37]Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank:
Extending Moore's Law via Computationally Error-Tolerant Computing. ACM Trans. Archit. Code Optim. 15(1): 8:1-8:27 (2018) - [c56]Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank:
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. HPCA 2018: 696-709 - [c55]Eric R. Hein, Tom Conte, Jeffrey Young, Srinivas Eswar, Jiajia Li, Patrick Lavin, Richard W. Vuduc, E. Jason Riedy:
An Initial Characterization of the Emu Chick. IPDPS Workshops 2018: 579-588 - [c54]Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang:
Tackling memory access latency through DRAM row management. MEMSYS 2018: 137-147 - [e10]Sorel Reisman, Sheikh Iqbal Ahamed, Claudio Demartini, Thomas M. Conte, Ling Liu, William R. Claycomb, Motonori Nakamura, Edmundo Tovar, Stelvio Cimato, Chung-Horng Lung, Hiroki Takakura, Ji-Jiang Yang, Toyokazu Akiyama, Zhiyong Zhang, Kamrul Hasan:
2018 IEEE 42nd Annual Computer Software and Applications Conference, COMPSAC 2018, Tokyo, Japan, 23-27 July 2018, Volume 1. IEEE Computer Society 2018, ISBN 978-1-5386-2667-2 [contents] - [e9]Sorel Reisman, Sheikh Iqbal Ahamed, Claudio Demartini, Thomas M. Conte, Ling Liu, William R. Claycomb, Motonori Nakamura, Edmundo Tovar, Stelvio Cimato, Chung-Horng Lung, Hiroki Takakura, Ji-Jiang Yang, Toyokazu Akiyama, Zhiyong Zhang, Md. Kamrul Hasan:
2018 IEEE 42nd Annual Computer Software and Applications Conference, COMPSAC 2018, Tokyo, Japan, 23-27 July 2018, Volume 2. IEEE Computer Society 2018 [contents] - [i4]Jeffrey Young, Eric R. Hein, Srinivas Eswar, Patrick Lavin, Jiajia Li, E. Jason Riedy, Richard W. Vuduc, Tom Conte:
A Microbenchmark Characterization of the Emu Chick. CoRR abs/1809.07696 (2018) - 2017
- [j36]Thomas M. Conte, Erik P. DeBenedictis, Paolo A. Gargini, Elie K. Track:
Rebooting Computing: The Road Ahead. Computer 50(1): 20-29 (2017) - [j35]Erik P. DeBenedictis, Mustafa Badaroglu, An Chen, Thomas M. Conte, Paolo A. Gargini:
Sustaining Moore's Law with 3D Chips. Computer 50(8): 69-73 (2017) - [j34]Jeffrey S. Vetter, Erik P. DeBenedictis, Thomas M. Conte:
Architectures for the Post-Moore Era. IEEE Micro 37(4): 6-8 (2017) - [c53]Erik P. DeBenedictis, Jeanine E. Cook, Sriseshan Srikanth, Thomas M. Conte:
Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C. HPEC 2017: 1-7 - [c52]Sriseshan Srikanth, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook:
The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing. ICRC 2017: 1-8 - [e8]Sorel Reisman, Sheikh Iqbal Ahamed, Claudio Demartini, Thomas M. Conte, Ling Liu, William R. Claycomb, Motonori Nakamura, Edmundo Tovar, Stelvio Cimato, Chung-Horng Lung, Hiroki Takakura, Ji-Jiang Yang, Toyokazu Akiyama, Zhiyong Zhang, Kamrul Hasan:
41st IEEE Annual Computer Software and Applications Conference, COMPSAC 2017, Turin, Italy, July 4-8, 2017. Volume 1. IEEE Computer Society 2017, ISBN 978-1-5386-0367-3 [contents] - [e7]Sorel Reisman, Sheikh Iqbal Ahamed, Claudio Demartini, Thomas M. Conte, Ling Liu, William R. Claycomb, Motonori Nakamura, Edmundo Tovar, Stelvio Cimato, Chung-Horng Lung, Hiroki Takakura, Ji-Jiang Yang, Toyokazu Akiyama, Zhiyong Zhang, Kamrul Hasan:
41st IEEE Annual Computer Software and Applications Conference, COMPSAC 2017, Turin, Italy, July 4-8, 2017. Volume 2. IEEE Computer Society 2017 [contents] - [i3]Thomas M. Conte, Erik P. DeBenedictis, R. Stanley Williams, Mark D. Hill:
Challenges to Keeping the Computer Industry Centered in the US. CoRR abs/1706.10267 (2017) - 2016
- [c51]Sapan Agarwal, Jeanine E. Cook, Erik DeBenedictis, Michael P. Frank, Gert Cauwenberghs, Sriseshan Srikanth, Bobin Deng, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte:
Energy efficiency limits of logic and memory. ICRC 2016: 1-8 - [c50]Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook:
Computationally-redundant energy-efficient processing for y'all (CREEPY). ICRC 2016: 1-8 - [c49]Rishiraj A. Bheda, Thomas M. Conte, Jeffrey S. Vetter:
Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging. MEMSYS 2016: 289-294 - [e6]Tom Conte, Yuanyuan Zhou:
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2016, Atlanta, GA, USA, April 2-6, 2016. ACM 2016, ISBN 978-1-4503-4091-5 [contents] - [i2]Sriseshan Srikanth, Bobin Deng, Thomas M. Conte:
A Brief Survey of Non-Residue Based Computational Error Correction. CoRR abs/1611.03099 (2016) - 2015
- [j33]Tom Conte:
A Time of Change. Computer 48(1): 4-6 (2015) - [j32]Thomas M. Conte:
The Computer Society Must Change. Computer 48(12): 9 (2015) - [j31]Thomas M. Conte, Elie K. Track, Erik DeBenedictis:
Rebooting Computing: New Strategies for Technology Scaling. Computer 48(12): 10-13 (2015) - [j30]Brian P. Railing, Eric R. Hein, Thomas M. Conte:
Contech: Efficiently Generating Dynamic Task Graphs for Arbitrary Parallel Programs. ACM Trans. Archit. Code Optim. 12(2): 25:1-25:24 (2015) - [c48]Yung-Hsiang Lu, Alan M. Kadin, Alexander C. Berg, Thomas M. Conte, Erik P. DeBenedictis, Rachit Garg, Ganesh Gingade, Bichlien Hoang, Yongzhen Huang, Boxun Li, Jingyu Liu, Wei Liu, Huizi Mao, Junran Peng, Tianqi Tang, Elie K. Track, Jingqiu Wang, Tao Wang, Yu Wang, Jun Yao:
Rebooting Computing and Low-Power Image Recognition Challenge. ICCAD 2015: 927-932 - 2014
- [c47]Jun Wang, Jesse G. Beu, Rishiraj A. Bheda, Tom Conte, Zhenjiang Dong, Chad D. Kersey, Mitchelle Rasquinha, George F. Riley, William J. Song, He Xiao, Peng Xu, Sudhakar Yalamanchili:
Manifold: A parallel simulation framework for multicore systems. ISPASS 2014: 106-115 - 2013
- [c46]Jesse G. Beu, Jason A. Poovey, Eric R. Hein, Thomas M. Conte:
High-speed formal verification of heterogeneous coherence hierarchies. HPCA 2013: 566-577 - 2012
- [c45]Paul D. Bryan, Jason A. Poovey, Jesse G. Beu, Thomas M. Conte:
Accelerating Multi-threaded Application Simulation through Barrier-Interval Time-Parallelism. MASCOTS 2012: 117-126 - [c44]Rishiraj A. Bheda, Jesse G. Beu, Brian P. Railing, Thomas M. Conte:
Extrapolation Pitfalls When Evaluating Limited Endurance Memory. MASCOTS 2012: 261-268 - [c43]Jun Wang, Jesse G. Beu, Sudhakar Yalamanchili, Tom Conte:
Designing Configurable, Modifiable and Reusable Components for Simulation of Multicore Systems. SC Companion 2012: 472-476 - 2011
- [c42]Rishiraj A. Bheda, Jason A. Poovey, Jesse G. Beu, Thomas M. Conte:
Energy efficient Phase Change Memory based main memory for future high performance systems. IGCC 2011: 1-8 - [c41]Jason A. Poovey, Brian P. Railing, Thomas M. Conte:
Parallel Pattern Detection for Architectural Improvements. HotPar 2011 - [c40]Jesse G. Beu, Michel C. Rosier, Thomas M. Conte:
Manager-client pairing: a framework for implementing coherence hierarchies. MICRO 2011: 226-236
2000 – 2009
- 2009
- [j29]Markus Levy, Thomas M. Conte:
Embedded Multicore Processors and Systems. IEEE Micro 29(3): 7-9 (2009) - [j28]Jason A. Poovey, Thomas M. Conte, Markus Levy, Shay Gal-On:
A Benchmark Characterization of the EEMBC Benchmark Suite. IEEE Micro 29(5): 18-29 (2009) - [c39]Balaji V. Iyer, Thomas M. Conte:
On power and energy trends of IEEE 802.11n PHY. MSWiM 2009: 353-356 - 2008
- [c38]Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte:
Energy-aware opcode design. ICCD 2008: 570-576 - [c37]Balaji V. Iyer, Thomas M. Conte:
A Power Model for Register-Sharing Structures. DIPES 2008: 131-142 - 2007
- [c36]Thomas M. Conte:
Keynote: Insight, Not (Random) Numbers: An Embedded Perspective. HiPEAC 2007: 3 - [c35]Paul D. Bryan, Thomas M. Conte:
Combining cluster sampling with single pass methods for efficient sampling regimen design. ICCD 2007: 472-479 - [c34]Paul D. Bryan, Michel C. Rosier, Thomas M. Conte:
Reverse State Reconstruction for Sampled Microarchitectural Simulation. ISPASS 2007: 190-199 - 2005
- [j27]Monther Aldwairi, Thomas M. Conte, Paul D. Franzon:
Configurable string matching hardware for speeding up intrusion detection. SIGARCH Comput. Archit. News 33(1): 99-107 (2005) - [j26]Saurabh Sharma, Jesse G. Beu, Thomas M. Conte:
Spectral prefetcher: An effective mechanism for L2 cache prefetching. ACM Trans. Archit. Code Optim. 2(4): 423-450 (2005) - [j25]Huiyang Zhou, Thomas M. Conte:
Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction. IEEE Trans. Computers 54(7): 897-912 (2005) - [j24]Emre Özer, Thomas M. Conte:
High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm. IEEE Trans. Parallel Distributed Syst. 16(12): 1132-1142 (2005) - [c33]Thomas M. Conte:
Insight, not (random) numbers. ISPASS 2005: 101 - [e5]Thomas M. Conte, Paolo Faraboschi, William H. Mangione-Smith, Walid A. Najjar:
Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005. ACM 2005, ISBN 1-59593-149-X [contents] - [e4]Thomas M. Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer:
High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings. Lecture Notes in Computer Science 3793, Springer 2005, ISBN 3-540-30317-0 [contents] - 2004
- [j23]Alessio Bechini, Thomas M. Conte, Cosimo Antonio Prete:
Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems. IEEE Micro 24(4): 8-9 (2004) - 2003
- [j22]Chao-ying Fu, Jill T. Bodine, Thomas M. Conte:
Modeling Value Speculation: An Optimal Edge Selection Problem. IEEE Trans. Computers 52(3): 277-292 (2003) - [j21]Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte:
Adaptive mode control: A static-power-efficient cache design. ACM Trans. Embed. Comput. Syst. 2(3): 347-372 (2003) - [c32]Huiyang Zhou, Thomas M. Conte:
Enhancing memory level parallelism via recovery-free value prediction. ICS 2003: 326-335 - [c31]Huiyang Zhou, Jill Flanagan, Thomas M. Conte:
Detecting Global Stride Locality in Value Streams. ISCA 2003: 324-335 - [e3]Jaime H. Moreno, Praveen K. Murthy, Thomas M. Conte, Paolo Faraboschi:
Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003. ACM 2003, ISBN 1-58113-676-5 [contents] - [e2]Richard Johnson, Tom Conte, Wen-mei W. Hwu:
1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA. IEEE Computer Society 2003, ISBN 0-7695-1913-X [contents] - 2002
- [j20]Thomas M. Conte:
Choosing the Brain(s) of an Embedded System. Computer 35(7): 106-107 (2002) - [c30]Huiyang Zhou, Thomas M. Conte:
Code Size Efficiency in Global Scheduling for ILP Processors. Interaction between Compilers and Computer Architectures 2002: 79-90 - 2001
- [c29]Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte:
Adaptive Mode Control: A Static-Power-Efficient Cache Design. IEEE PACT 2001: 61-70 - [c28]Emre Özer, Thomas M. Conte, Saurabh Sharma:
Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors. HiPC 2001: 192-203 - [c27]Huiyang Zhou, Matthew D. Jennings, Thomas M. Conte:
Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. LCPC 2001: 223-238 - 2000
- [j19]Thomas M. Conte, Sumedh W. Sathaye:
Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility. IEEE Trans. Computers 49(8): 814-825 (2000) - [j18]Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen:
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 129-137 (2000) - [c26]Kim M. Hazelwood, Thomas M. Conte:
A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization. IEEE PACT 2000: 71-80
1990 – 1999
- 1999
- [j17]Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman:
Editor's Introduction. Int. J. Parallel Program. 27(5): 325-326 (1999) - [j16]Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman:
Editors' Introduction. Int. J. Parallel Program. 27(6): 425-426 (1999) - [j15]Pradip Bose, Thomas M. Conte, Todd M. Austin:
Challenges in processor modeling and validation [Guest Editors?? introduction]. IEEE Micro 19(3): 9-14 (1999) - [c25]Mouna Nakkar, David G. Bentlage, John Harding, David Schwartz, Paul D. Franzon, Thomas M. Conte:
Dynamically Programmable Cache Evaluation and Virtualization. FPGA 1999: 246 - [c24]Sergei Y. Larin, Thomas M. Conte:
Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. MICRO 1999: 82-92 - 1998
- [j14]Pradip Bose, Thomas M. Conte:
Performance Analysis and Its Impact on Design. Computer 31(5): 41-49 (1998) - [j13]Matthew D. Jennings, Thomas M. Conte:
Subword extensions for video processing on mobile systems. IEEE Concurr. 6(3): 13-16 (1998) - [j12]Thomas M. Conte, Mary Ann Hirsch, Wen-mei W. Hwu:
Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation. IEEE Trans. Computers 47(6): 714-720 (1998) - [j11]Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte:
MPS: Miss-Path Scheduling for Multiple-Issue Processors. IEEE Trans. Computers 47(12): 1382-1397 (1998) - [c23]Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte:
A Fast Interrupt Handling Scheme for VLIW Processors. IEEE PACT 1998: 136-141 - [c22]Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte:
Value Speculation Scheduling for High Performance Processors. ASPLOS 1998: 262-271 - [c21]William A. Havanki, Sanjeev Banerjia, Thomas M. Conte:
Treegion Scheduling for Wide Issue Processors. HPCA 1998: 266-276 - [c20]Emre Özer, Sanjeev Banerjia, Thomas M. Conte:
Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. MICRO 1998: 308-315 - 1997
- [j10]Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe:
Challenges to Combining General-Purpose and Multimedia Processors. Computer 30(12): 33-37 (1997) - [j9]Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson:
Compilers for Instruction-Level Parallelism. Computer 30(12): 63-69 (1997) - [j8]Thomas M. Conte, Sumedh W. Sathaye:
Optimization of VLIW compatibility systems employing dynamic rescheduling. Int. J. Parallel Program. 25(2): 83-112 (1997) - [c19]Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte:
Path Prediction for High Issue-Rate Processors. IEEE PACT 1997: 178-188 - [c18]Sanjeev Banerjia, William A. Havanki, Thomas M. Conte:
Treegion Scheduling for Highly Parallel Processors. Euro-Par 1997: 1074-1078 - [c17]Thomas M. Conte, Andrew Wolfe:
Combining General-Purpose and Multimedia in One Package: Challenges and Opportunities. HICSS (1) 1997: 708-712 - [e1]Mark Smotherman, Tom Conte:
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997. ACM/IEEE Computer Society 1997, ISBN 0-8186-7977-8 [contents] - 1996
- [j7]Thomas M. Conte:
Importance of Profiling and Compatibility. ACM Comput. Surv. 28(4es): 26 (1996) - [j6]Thomas M. Conte, Burzin A. Patel, Kishore N. Menezes, J. Stan Cox:
Hardware-Based Profiling: An Effective Technique for Profile-Driven Optimization. Int. J. Parallel Program. 24(2): 187-206 (1996) - [c16]Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes:
Reducing State Loss For Effective Trace Sampling of Superscalar Processors. ICCD 1996: 468-477 - [c15]Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia:
A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. MICRO 1996: 4-13 - [c14]Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch:
Accurate and Practical Profile-driven Compilation Using the Profile Buffer. MICRO 1996: 36-45 - [c13]Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye:
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. MICRO 1996: 201-211 - [c12]Ashutosh Singla, Thomas M. Conte:
Bipartitioning for Hybrid FPGA-Software Simulatio. VLSI Design 1996: 211-214 - 1995
- [j5]Thomas M. Conte, Wen-mei W. Hwu:
Advances in Benchmarking Techniques: New Standards and Quantitative Metrics. Adv. Comput. 41: 231-253 (1995) - [c11]J. Stan Cox, David P. Howell, Thomas M. Conte:
Commercializing profile-driven optimization. HICSS (1) 1995: 221-228 - [c10]Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye:
A technique to determine power-efficient, high-performance superscalar processors. HICSS (1) 1995: 324-333 - [c9]Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel:
Optimization of Instruction Fetch Mechanisms for High Issue Rates. ISCA 1995: 333-344 - [c8]Thomas M. Conte, Sumedh W. Sathaye:
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. MICRO 1995: 208-218 - 1994
- [j4]Wen-mei W. Hwu, Thomas M. Conte:
The Susceptibility of Programs to Context Switching. IEEE Trans. Computers 43(9): 994-1003 (1994) - [c7]Thomas M. Conte, Charles E. Gimarc:
Fast Simulation of Computer Architectures: Introduction. HICSS (1) 1994: 184 - [c6]Thomas M. Conte, Burzin A. Patel, J. Stan Cox:
Using branch handling hardware to support profile-driven optimization. MICRO 1994: 12-21 - 1993
- [j3]William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu:
The Effect of Code Expanding Optimizations on Instruction Cache Design. IEEE Trans. Computers 42(9): 1045-1057 (1993) - [c5]Thomas M. Conte, William H. Mangione-Smith:
Determining Cost-Effective Multiple Issue Processor Designs. ICCD 1993: 94-101 - 1992
- [b1]Thomas M. Conte:
Systematic Computer Architecture Prototyping. University of Illinois Urbana-Champaign, USA, 1992 - [c4]Thomas M. Conte:
Tradeoffs in processor/memory interfaces for superscalar processors. MICRO 1992: 202-205 - [c3]Thomas M. Conte, Wen-mei W. Hwu:
Systematic prototyping of superscalar computer architectures. RSP 1992: 161-170 - 1991
- [j2]Thomas M. Conte, Wen-mei W. Hwu:
Benchmark Characterization. Computer 24(1): 48-56 (1991) - [j1]Thomas M. Conte, Wen-mei W. Hwu:
A brief survey of benchmark usage in the architecture community. SIGARCH Comput. Archit. News 19(4): 37-44 (1991)
1980 – 1989
- 1989
- [c2]Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang:
Comparing Software and Hardware Schemes For Reducing the Cost of Branches. ISCA 1989: 224-233 - [c1]Wen-mei W. Hwu, Thomas M. Conte:
A Simulation Study of Simultaneous Vector Prefetch Performance in Multiprocessor Memory Subsystems (Extended Abstract). SIGMETRICS 1989: 227 - 1984
- [i1]David J. Farber, Gary S. Delp, Thomas M. Conte:
Thinwire protocol for connecting personal computers to the Internet. RFC 914: 1-22 (1984)
Coauthor Index
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