A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology - Dong-Myung Choi; Yikui Dong; Roan Nicholson; Frank Liu; Wenyan Jia; Vadim Levin; Mike He; Sameer Pradhan; Jieqiong Du; Michael De Vita; Amanda Tran; Reza Navid; et al. (IEEE Symposium on VLSI Technology and Circuits 2024, Honolulu, HI, USA, June 16-20, 2024, 2024)

A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe PHY in 10nm FinFET CMOS - Shenggao Li; Fulvio Spagna; Ji Chen; Xiaoqing Wang; Luke Tong; Sujatha Gowder; Wenyan Jia; Roan Nicholson; Sitaraman Iyer; Rui Song; Lily Li; Meng-hung Chen; et al. (IEEE Asian Solid-State Circuits Conference, A-SSCC 2018, Tainan, Taiwan, November 5-7, 2018, 2018)

A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS - Fulvio Spagna; Lidong Chen; Mamatha Deshpande; Yongping Fan; Doug Gambetta; Sujatha Gowder; Sitaraman Iyer; Rohit Kumar; Peter Kwok; Renuka Krishnamurthy; Chien-chun Lin; Ravindran Mohanavelu; et al. (IEEE International Solid-State Circuits Conference, ISSCC 2010, Digest of Technical Papers, San Francisco, CA, USA, 7-11 February, 2010, 2010)

Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery - Sudeep Puligundla; Fulvio Spagna; Lidong Chen; Amanda Tran (2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, 2010)