European Test Symposium Teams: an Anniversary Snapshot. - Jenihhin, Maksim; Raik, Jaan; Jutman, Artur; Cherezova, Natalia; Ubar, Raimund; Miclea, Liviu; Enyedi, Szilárd; Stefan, I.; Stan, Ovidiu; Corches, Cosmina; Peng, Z.; Eles, Petru; et al. (2025)

Dual Use Circuitry for Early Failure Warning and Test. - Coyle, Alexander; Jiang, Hui; Dworak, Jennifer; Manikas, Theodore W.; Nepal, Kundan (2024)

Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift. - Jiang, Hui; Zhang, Fanchen; Dworak, Jennifer; Nepal, Kundan; Manikas, Theodore W. (J. Electron. Test., 2023)

Harvesting Wasted Clock Cycles for Efficient Online Testing. - Yassien, Eslam; Xu, Yongjia; Jiang, Hui; Nguyen, Thach; Dworak, Jennifer; Manikas, Theodore W.; Nepal, Kundan (2023)

Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis. - Rupanetti, Dulana; Salamy, Hassan A.; Min, Cheol-Hong; Nepal, Kundan (Int. J. Parallel Emergent Distributed Syst., 2022)

3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations. - Alhelaly, Soha; Dworak, Jennifer; Nepal, Kundan; Manikas, Theodore W.; Gui, Ping; Crouch, Alfred L. (IEEE Trans. Emerg. Top. Comput., 2021)

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. - Sun, Yi; Jiang, Hui; Ramakrishnan, Lakshmi; Dworak, Jennifer; Nepal, Kundan; Manikas, Theodore W.; Bahar, R. Iris (2021)

Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications. - Rupanetti, Dulana; Nepal, Kundan; Salamy, Hassan A.; Min, Cheol-Hong (2020)

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. - Sun, Yi; Zhang, Fanchen; Jiang, Hui; Nepal, Kundan; Dworak, Jennifer; Manikas, Theodore W.; Bahar, R. Iris (J. Electron. Test., 2019)

True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors. - Hellkamp, Daniel; Nepal, Kundan (J. Circuits Syst. Comput., 2019)

Low cost Brussels sprouts harvester for small farms. - Audi, Milad; Frost, William; Henriquez, Jose; Jones, Nathan; Hang, Janssen; Nepal, Kundan (2019)

Low-cost instrumentation of high-tunnels for a small co-op farm. - Ziemer, Jeremy; Stokes, Austin; Hang, Janssen; Nepal, Kundan (2019)

Dilated Temporal Convolutional Neural Network Architecture with Independent Component Layer for Human Activity Recognition. - Ward, Matthew; Min, Cheol-Hong; Salamy, Hassan A.; Nepal, Kundan (2019)

Test Architecture for Fine Grained Capture Power Reduction. - Sun, Yi; Jiang, Hui; Ramakrishnan, Lakshmi; Segal, Matan; Nepal, Kundan; Dworak, Jennifer; Manikas, Theodore W.; Bahar, R. Iris (2019)

Tools for the 3Cs of Entrepreneurially Minded Learning (EML). - LeBlanc, Heath J.; Nepal, Kundan; Mowry, Greg S.; Cheville, Alan (2018)

Stimulating curiosity and the ability to formulate technical questions in an electric circuits course using the question formulation technique (QFT). - LeBlanc, Heath J.; Nepal, Kundan; Mowry, Greg S. (2017)

Combinational hardware Trojan detection using logic implications. - Cornell, Noah; Nepal, Kundan (2017)

Detecting a trojan die in 3D stacked integrated circuits. - Alhelaly, Soha; Dworak, Jennifer; Manikas, Theodore W.; Gui, Ping; Nepal, Kundan; Crouch, Alfred L. (2017)

Using Existing Reconfigurable Logic in 3D Die Stacks for Test. - Zhang, Fanchen; Sun, Yi; Shen, Xi; Nepal, Kundan; Dworak, Jennifer; Manikas, Theodore W.; Gui, Ping; Bahar, R. Iris; Crouch, Al; Potter, John C. (2016)

Repairing a 3-D Die-Stack Using Available Programmable Logic. - Nepal, Kundan; Alhelaly, Soha; Dworak, Jennifer; Bahar, R. Iris; Manikas, Theodore W.; Guikundan, Ping (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Built-in Self-Repair in a 3D die stack using programmable logic. - Nepal, Kundan; Shen, Xi; Dworak, Jennifer; Manikas, Theodore W.; Bahar, R. Iris (2013)

Using implications to choose tests through suspect fault identification. - Dworak, Jennifer; Nepal, Kundan; Alves, Nuno; Shi, Yiwen; Imbriglia, Nicholas; Bahar, R. Iris (ACM Trans. Design Autom. Electr. Syst., 2012)

Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors. - Nepal, Kundan (2012)

Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults. - Dunbar, Carson; Nepal, Kundan (J. Comput., 2011)

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. - Alves, Nuno; Shi, Yiwen; Imbriglia, Nicholas; Dworak, Jennifer; Nepal, Kundan; Bahar, R. Iris (2011)

Wow! linear systems and signal processing is fun! - Aburdene, Maurice F.; Nepal, Kundan (2011)

Enhancing online error detection through area-efficient multi-site implications. - Alves, Nuno; Shi, Yiwen; Dworak, Jennifer; Bahar, R. Iris; Nepal, Kundan (2011)

A Cost Effective Approach for Online Error Detection Using Invariant Relationships. - Alves, Nuno; Buben, Alison; Nepal, Kundan; Dworak, Jennifer; Bahar, R. Iris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Improving the testability and reliability of sequential circuits with invariant logic. - Alves, Nuno; Nepal, Kundan; Dworak, Jennifer; Bahar, R. Iris (2010)

Detecting errors using multi-cycle invariance information. - Alves, Nuno; Nepal, Kundan; Dworak, Jennifer; Bahar, R. Iris (2009)

Compacting test vector sets via strategic use of implications. - Alves, Nuno; Dworak, Jennifer; Bahar, R. Iris; Nepal, Kundan (2009)

Using Implications for Online Error Detection. - Nepal, Kundan; Alves, Nuno; Dworak, Jennifer; Bahar, R. Iris (2008)

Designing Nanoscale Logic Circuits Based on Markov Random Fields. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (J. Electron. Test., 2007)

Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (2007)

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (IEEE Micro, 2006)

Timing analysis for full-custom circuits using symbolic DC formulations. - Song, Hui-Yuan; Nepal, Kundan; Bahar, R. Iris; Grodstein, Joel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Designing MRF based error correcting circuits for memory elements. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (2006)

Optimizing noise-immune nanoscale circuits using principles of Markov random fields. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (2006)

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. - Bahar, R. Iris; Song, Hui-Yuan; Nepal, Kundan; Grodstein, Joel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Designing logic circuits for probabilistic computation in the presence of noise. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (2005)

Design evolution of the Trinity College IGVC robot ALVIN. - Bovard, Michelle; Gillette, Matthew; Lanerolle, Trishan R. de; Marinkovic, Bozidar; Trinh, Nhon H.; Votto, Peter; Ahlgren, David J.; Nepal, Kundan; Tamrakar, Amir (J. Field Robotics, 2004)

RESTA: a robust and extendable symbolic timing analysis tool. - Nepal, Kundan; Song, Hui-Yuan; Bahar, R. Iris; Grodstein, Joel (2004)