Dual Use Circuitry for Early Failure Warning and Test - Alexander Coyle; Hui Jiang; Jennifer Dworak; Theodore W. Manikas; Kundan Nepal (25th International Symposium on Quality Electronic Design, ISQED 2024, San Francisco, CA, USA, April 3-5, 2024, 2024)

Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift - Hui Jiang; Fanchen Zhang; Jennifer Dworak; Kundan Nepal; Theodore W. Manikas (J. Electron. Test., 2023)

Harvesting Wasted Clock Cycles for Efficient Online Testing - Eslam Yassien; Yongjia Xu; Hui Jiang; Thach Nguyen; Jennifer Dworak; Theodore W. Manikas; Kundan Nepal (IEEE European Test Symposium, ETS 2023, Venezia, Italy, May 22-26, 2023, 2023)

Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis - Dulana Rupanetti; Hassan A. Salamy; Cheol-Hong Min; Kundan Nepal (Int. J. Parallel Emergent Distributed Syst., 2022)

3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations - Soha Alhelaly; Jennifer Dworak; Kundan Nepal; Theodore W. Manikas; Ping Gui; Alfred L. Crouch (IEEE Trans. Emerg. Top. Comput., 2021)

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits - Yi Sun; Hui Jiang; Lakshmi Ramakrishnan; Jennifer Dworak; Kundan Nepal; Theodore W. Manikas; R. Iris Bahar (IEEE International Test Conference, ITC 2021, Anaheim, CA, USA, October 10-15, 2021, 2021)

Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications - Dulana Rupanetti; Kundan Nepal; Hassan A. Salamy; Cheol-Hong Min (10th Annual Computing and Communication Workshop and Conference, CCWC 2020, Las Vegas, NV, USA, January 6-8, 2020, 2020)

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack - Yi Sun; Fanchen Zhang; Hui Jiang; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (J. Electron. Test., 2019)

True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors - Daniel Hellkamp; Kundan Nepal (J. Circuits Syst. Comput., 2019)

Low cost Brussels sprouts harvester for small farms - Milad Audi; William Frost; Jose Henriquez; Nathan Jones; Janssen Hang; Kundan Nepal (IEEE Global Humanitarian Technology Conference, GHTC 2019, Seattle, WA, USA, October 17-20, 2019, 2019)

Low-cost instrumentation of high-tunnels for a small co-op farm - Jeremy Ziemer; Austin Stokes; Janssen Hang; Kundan Nepal (IEEE Global Humanitarian Technology Conference, GHTC 2019, Seattle, WA, USA, October 17-20, 2019, 2019)

Dilated Temporal Convolutional Neural Network Architecture with Independent Component Layer for Human Activity Recognition - Matthew Ward; Cheol-Hong Min; Hassan A. Salamy; Kundan Nepal (26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019, 2019)

Test Architecture for Fine Grained Capture Power Reduction - Yi Sun; Hui Jiang; Lakshmi Ramakrishnan; Matan Segal; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019, 2019)

Tools for the 3Cs of Entrepreneurially Minded Learning (EML) - Heath J. LeBlanc; Kundan Nepal; Greg S. Mowry; Alan Cheville (IEEE Frontiers in Education Conference, FIE 2018, San Jose, CA, USA, October 3-6, 2018, 2018)

Stimulating curiosity and the ability to formulate technical questions in an electric circuits course using the question formulation technique (QFT) - Heath J. LeBlanc; Kundan Nepal; Greg S. Mowry (2017 IEEE Frontiers in Education Conference, FIE 2017, Indianapolis, IN, USA, October 18-21, 2017, 2017)

Combinational hardware Trojan detection using logic implications - Noah Cornell; Kundan Nepal (IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, 2017)

Detecting a trojan die in 3D stacked integrated circuits - Soha Alhelaly; Jennifer Dworak; Theodore W. Manikas; Ping Gui; Kundan Nepal; Alfred L. Crouch (2017 IEEE North Atlantic Test Workshop, NATW 2017, Providence, RI, USA, May 8-10, 2017, 2017)

Using Existing Reconfigurable Logic in 3D Die Stacks for Test - Fanchen Zhang; Yi Sun; Xi Shen; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; Ping Gui; R. Iris Bahar; Al Crouch; John C. Potter (25th IEEE North Atlantic Test Workshop, NATW 2016, Providence, RI, USA, May 9-11, 2016, 2016)

Repairing a 3-D Die-Stack Using Available Programmable Logic - Kundan Nepal; Soha Alhelaly; Jennifer Dworak; R. Iris Bahar; Theodore W. Manikas; Ping Guikundan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Built-in Self-Repair in a 3D die stack using programmable logic - Kundan Nepal; Xi Shen; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013)

Using implications to choose tests through suspect fault identification - Jennifer Dworak; Kundan Nepal; Nuno Alves; Yiwen Shi; Nicholas Imbriglia; R. Iris Bahar (ACM Trans. Design Autom. Electr. Syst., 2012)

Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors - Kundan Nepal (10th IEEE International NEWCAS Conference, Montreal, QC, Canada, June 17-20, 2012, 2012)

Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults - Carson Dunbar; Kundan Nepal (J. Comput., 2011)

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis - Nuno Alves; Yiwen Shi; Nicholas Imbriglia; Jennifer Dworak; Kundan Nepal; R. Iris Bahar (16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011)

Wow! linear systems and signal processing is fun! - Maurice F. Aburdene; Kundan Nepal (2011 Frontiers in Education Conference, FIE 2011, Rapid City, SD, USA, October 12-15, 2011, 2011)

Enhancing online error detection through area-efficient multi-site implications - Nuno Alves; Yiwen Shi; Jennifer Dworak; R. Iris Bahar; Kundan Nepal (29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, 2011)

A Cost Effective Approach for Online Error Detection Using Invariant Relationships - Nuno Alves; Alison Buben; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Improving the testability and reliability of sequential circuits with invariant logic - Nuno Alves; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, 2010)

Detecting errors using multi-cycle invariance information - Nuno Alves; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009)

Compacting test vector sets via strategic use of implications - Nuno Alves; Jennifer Dworak; R. Iris Bahar; Kundan Nepal (2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009, 2009)

Using Implications for Online Error Detection - Kundan Nepal; Nuno Alves; Jennifer Dworak; R. Iris Bahar (2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008)

Designing Nanoscale Logic Circuits Based on Markov Random Fields - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (J. Electron. Test., 2007)

Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, 2007)

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (IEEE Micro, 2006)

Timing analysis for full-custom circuits using symbolic DC formulations - Hui-Yuan Song; Kundan Nepal; R. Iris Bahar; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Designing MRF based error correcting circuits for memory elements - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, 2006)

Optimizing noise-immune nanoscale circuits using principles of Markov random fields - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, 2006)

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing - R. Iris Bahar; Hui-Yuan Song; Kundan Nepal; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Designing logic circuits for probabilistic computation in the presence of noise - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, 2005)

Design evolution of the Trinity College IGVC robot ALVIN - Michelle Bovard; Matthew Gillette; Trishan R. de Lanerolle; Bozidar Marinkovic; Nhon H. Trinh; Peter Votto; David J. Ahlgren; Kundan Nepal; Amir Tamrakar (J. Field Robotics, 2004)

RESTA: a robust and extendable symbolic timing analysis tool - Kundan Nepal; Hui-Yuan Song; R. Iris Bahar; Joel Grodstein (Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, 2004)