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2020 – today
- 2021
[j2]Pascal Vivet
, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, César Fuguet Tortolero, Ivan Miro-Panades, Guillaume Moritz, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. IEEE J. Solid State Circuits 56(1): 79-97 (2021)- 2020
- [c11]Pascal Vivet, Eric Guthmuller, Yvain Thonnart, Gaël Pillonnet, Guillaume Moritz, Ivan Miro-Panades, César Fuguet Tortolero, Jean Durupt, Christian Bernard, Didier Varreau, Julian J. H. Pontes, Sébastien Thuries, David Coriat, Michel Harrand, Denis Dutoit, Didier Lattard, Lucile Arnaud, Jean Charbonnier, Perceval Coudrain, Arnaud Garnier, Frédéric Berger, Alain Gueugnot, Alain Greiner, Quentin L. Meunier, Alexis Farcy, Alexandre Arriordaz, Séverine Cheramy, Fabien Clermidy:
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. ISSCC 2020: 46-48
2010 – 2019
- 2019
- [c10]Imed Jani, Didier Lattard, Pascal Vivet, Jean Durupt, Sébastien Thuries, Edith Beigné:
Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning. ETS 2019: 1-2 - 2018
- [c9]Eric Guthmuller, César Fuguet Tortolero, Pascal Vivet, Christian Bernard, Ivan Miro Panades, Jean Durupt, E. Beignc, Didier Lattard, Séverine Cheramy, Alain Greiner, Quentin L. Meunier, Pirouz Bazargan-Sabet:
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. ESSCIRC 2018: 318-321 - 2016
- [c8]Jean Durupt, Pascal Vivet, Juergen Schloeffel:
IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system. ETS 2016: 1-6
2000 – 2009
- 2009
- [j1]Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach:
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application. IET Comput. Digit. Tech. 3(5): 487-500 (2009) - 2008
- [c7]Carolynn Bernier, Frédéric Hameau, Gérard Billiot, Emeric de Foucauld, Stéphanie Robinet, Didier Lattard, Jean Durupt, Francois Dehmas, Laurent Ouvry, Pierre Vincent:
An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications. ESSCIRC 2008: 426-429 - [c6]Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach:
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. NOCS 2008: 149-158 - 2007
- [c5]Didier Lattard, Edith Beigné, Christian Bernard, Catherine Bour, Fabien Clermidy, Yves Durand, Jean Durupt, Didier Varreau, Pascal Vivet, Pierre Penard, Arnaud Bouttier, Friedbert Berens:
A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. ISSCC 2007: 258-601 - [c4]Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach:
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip. NOCS 2007: 216 - 2006
- [c3]Xuan-Tu Tran, Vincent Beroulle, Jean Durupt, Chantal Robach, François Bertrand:
Design-for-Test of Asynchronous Networks-on-Chip. DDECS 2006: 163-167 - [c2]Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach:
A DFT Architecture for Asynchronous Networks-on-Chip. ETS 2006: 219-224
1990 – 1999
- 1993
- [c1]J.-M. Libs, B. Siaud, Jean Durupt, Bernard Boutherin, Gilles Jacquemod, Michel Le Helley:
Experimental multiprocessor architecture dedicated for solving 3D PDEs. PDP 1993: 71-77
Coauthor Index
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