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ORCIDYusuke Matsushita 0001
Person information
- affiliation: Keio University, Japan
Other persons with the same name
- Yusuke Matsushita 0002
![[0000-0002-5208-3106]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-5208-3106")
— University of Tokyo, Japan - Yusuke Matsushita 0003 — Wakayama University, Japan
- Yusuke Matsushita 0004 — Kyoto Institute of Technology, Department of Mechanical Engineering, Japan
- Yusuke Matsushita 0005 — Toyohashi University of Technology, Aichi, Japan
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2010 – 2019
- 2019
[c4]Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hideharu Amano:
Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA. FPL 2019: 411-412- 2018
- [j2]Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano:
Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. Int. J. Netw. Comput. 8(1): 124-139 (2018) - 2017
- [j1]Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano:
Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator. IEICE Trans. Inf. Syst. 100-D(12): 2828-2836 (2017) - [c3]Nguyen Anh Vu Doan, Yusuke Matsushita, Naoki Ando, Hayate Okuhara, Hideharu Amano:
Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA. MCSoC 2017: 143-150 - 2016
- [c2]Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano:
Body bias grain size exploration for a coarse grained reconfigurable accelerator. FPL 2016: 1-4 - [c1]Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano:
Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. CANDAR 2016: 195-201
Coauthor Index
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