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ORCIDShunichi Kaeriyama
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2010 – 2019
- 2015
[c5]Ken Chang, Shunichi Kaeriyama:
Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links: Wireline subcommittee. ISSCC 2015: 50-51- 2012
- [j6]Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno:
A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. IEEE J. Solid State Circuits 47(2): 435-443 (2012) - [c4]Gerrit den Besten, Shunichi Kaeriyama:
High-speed wireline transceivers and clocking. CICC 2012: 1-2 - 2011
- [j5]Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno:
A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests. IEICE Trans. Electron. 94-C(1): 102-109 (2011)
2000 – 2009
- 2009
- [j4]Shunichi Kaeriyama, Yasushi Amamiya, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara:
A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems. IEEE J. Solid State Circuits 44(12): 3568-3579 (2009) - [c3]Yasushi Amamiya, Shunichi Kaeriyama, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara:
A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems. ISSCC 2009: 358-359 - 2007
- [c2]Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno:
A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability. ISSCC 2007: 174-594 - 2006
- [j3]Naoki Banno, Toshitsugu Sakamoto, Noriyuki Iguchi, Hisao Kawaura, Shunichi Kaeriyama, Masayuki Mizuno, Kazuya Terabe
, Tsuyoshi Hasegawa, Masakazu Aono:
Solid-Electrolyte Nanometer Switch. IEICE Trans. Electron. 89-C(11): 1492-1498 (2006) - 2005
- [j2]Shunichi Kaeriyama, Toshitsugu Sakamoto, Hiroshi Sunamura, Masayuki Mizuno, Hisao Kawaura, Tsuyoshi Hasegawa, Kazuya Terabe, Tomonobu Nakayama, Masakazu Aono:
A nonvolatile programmable solid-electrolyte nanometer switch. IEEE J. Solid State Circuits 40(1): 168-176 (2005) - [j1]Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama:
Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic. J. Multiple Valued Log. Soft Comput. 11(5-6): 619-632 (2005) - 2000
- [c1]Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama:
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic. ISMVL 2000: 438-446
Coauthor Index
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