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ORCIDDaisuke Fujimoto
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2020 – today
- 2024
[j14]Junichi Sakamoto
, Daisuke Fujimoto, Riku Anzai, Naoki Yoshida, Tsutomu Matsumoto:
High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications. IEEE Trans. Very Large Scale Integr. Syst. 32(8): 1498-1511 (2024)- 2023
- [c20]Hikaru Nishiyama, Daisuke Fujimoto, Yu-ichi Hayashi:
Remote Fault Injection Attack against Cryptographic Modules via Intentional Electromagnetic Interference from an Antenna. ASHES@CCS 2023: 93-102 - 2022
- [j13]Junichi Sakamoto, Shungo Hayashi, Daisuke Fujimoto, Tsutomu Matsumoto:
Constructing software countermeasures against instruction manipulation attacks: an approach based on vulnerability evaluation using fault simulator. Clust. Comput. 25(4): 2739-2753 (2022) - 2021
- [j12]Shinichi Kawamura, Yuichi Komano, Hideo Shimizu, Saki Osuka, Daisuke Fujimoto, Yu-ichi Hayashi, Kentaro Imafuku:
Efficient Algorithms for Sign Detection in RNS Using Approximate Reciprocals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(1): 121-134 (2021) - 2020
- [j11]Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto:
Laser-Induced Controllable Instruction Replacement Fault Attack. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(1): 11-20 (2020) - [c19]Junichi Sakamoto, Shungo Hayashi, Daisuke Fujimoto, Tsutomu Matsumoto:
How to Code Data Integrity Verification Secure Against Single-Spot-Laser-Induced Instruction Manipulation Attacks. AICCSA 2020: 1-8 - [c18]Jurica Kundrata, Daisuke Fujimoto, Yu-ichi Hayashi, Adrijan Baric:
Comparison of Pearson correlation coefficient and distance correlation in Correlation Power Analysis on Digital Multiplier. MIPRO 2020: 146-151
2010 – 2019
- 2019
- [j10]Daisuke Fujimoto, Takashi Narimatsu, Yu-ichi Hayashi:
Fundamental Study on the Effects of Connector Torque Value on the Change of Inductance at the Contact Boundary. IEICE Trans. Electron. 102-C(9): 636-640 (2019) - [j9]Masahiro Kinugawa, Daisuke Fujimoto, Yu-ichi Hayashi:
Electromagnetic Information Extortion from Electronic Devices Using Interceptor and Its Countermeasure. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019(4): 62-90 (2019) - [c17]Junichi Sakamoto, Yusuke Nagahama, Daisuke Fujimoto, Yota Okuaki, Tsutomu Matsumoto:
Low-Latency Pairing Processor Architecture Using Fully-Unrolled Quotient Pipelining Montgomery Multiplier. AsianHOST 2019: 1-6 - [c16]Arthur Beckers, Masahiro Kinugawa, Yu-ichi Hayashi, Daisuke Fujimoto, Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede:
Design Considerations for EM Pulse Fault Injection. CARDIS 2019: 176-192 - 2018
- [j8]Daisuke Fujimoto, Shota Nin, Yu-ichi Hayashi, Noriyuki Miura, Makoto Nagata, Tsutomu Matsumoto:
A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1320-1324 (2018) - 2017
- [j7]Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura, Naofumi Homma, Yu-ichi Hayashi, Kazuo Sakiyama:
Protecting cryptographic integrated circuits with side-channel information. IEICE Electron. Express 14(2): 20162005 (2017) - [j6]Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Takafumi Aoki:
Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks. J. Cryptol. 30(2): 373-391 (2017) - 2016
- [c15]Junichi Sakamoto, Daisuke Fujimoto, Tsutomu Matsumoto:
Laser irradiation on EEPROM sense amplifiers enhances side-channel leakage of read bits. AsianHOST 2016: 1-6 - [c14]Daisuke Fujimoto, Yusuke Nagahama, Tsutomu Matsumoto:
How to design hardware prime field multipliers for bilinear pairing. ISOCC 2016: 203-204 - [i2]Daisuke Fujimoto, Shivam Bhasin, Makoto Nagata, Jean-Luc Danger:
A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version). IACR Cryptol. ePrint Arch. 2016: 522 (2016) - 2015
- [j5]Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata:
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan. IEEE J. Solid State Circuits 50(11): 2741-2749 (2015) - [j4]Sho Endo, Yang Li, Naofumi Homma, Kazuo Sakiyama, Kazuo Ohta, Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Jean-Luc Danger, Takafumi Aoki:
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1429-1438 (2015) - [c13]Daisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata:
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor. ASP-DAC 2015: 26-27 - [c12]Daisuke Fujimoto, Makoto Nagata, Shivam Bhasin, Jean-Luc Danger:
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement. ASP-DAC 2015: 749-754 - [c11]Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata, Naofumi Homma, Yu-ichi Hayashi, Takafumi Aoki:
EM attack sensor: concept, circuit, and design-automation methodology. DAC 2015: 176:1-176:6 - 2014
- [j3]Daisuke Fujimoto, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Yohei Hori, Toshihiro Katashita, Kazuo Sakiyama, Thanh-Ha Le, Julien Bringer, Pirouz Bazargan-Sabet, Shivam Bhasin, Jean-Luc Danger:
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage. IEICE Trans. Electron. 97-C(4): 272-279 (2014) - [c10]Noriyuki Miura, Daisuke Fujimoto, Rie Korenaga, Kohei Matsuda, Makoto Nagata:
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor. A-SSCC 2014: 225-228 - [c9]Makoto Nagata, Daisuke Fujimoto, Noriyuki Miura:
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips. ATS 2014: 258-262 - [c8]Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki:
EM Attack Is Non-invasive? - Design Methodology and Validity Verification of EM Attack Sensor. CHES 2014: 1-16 - [c7]Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata:
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS@DATE 2014: 13 - [c6]Daisuke Fujimoto, Daichi Tanaka, Noriyuki Miura, Makoto Nagata, Yu-ichi Hayashi, Naofumi Homma, Shivam Bhasin, Jean-Luc Danger:
Side-channel leakage on silicon substrate of CMOS cryptographic chip. HOST 2014: 32-37 - [c5]Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata:
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. ISSCC 2014: 216-217 - [c4]Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata:
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. VLSIC 2014: 1-2 - [i1]Naofumi Homma, Yu-ichi Hayashi, Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Makoto Nagata, Takafumi Aoki:
EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor. IACR Cryptol. ePrint Arch. 2014: 541 (2014) - 2013
- [j2]Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata:
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2533-2541 (2013) - 2011
- [c3]Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh:
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST 2011: 87-92 - 2010
- [j1]Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata:
An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. IEICE Trans. Electron. 93-C(6): 820-826 (2010)
2000 – 2009
- 2009
- [c2]Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata:
A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. CICC 2009: 187-190 - 2003
- [c1]Sadao Kawamura, Katsuya Kanaoka, Yuichiro Nakayama, Jinwoo Jeon, Daisuke Fujimoto:
Improvement of passive elements for wearable haptic displays. ICRA 2003: 816-821
Coauthor Index
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