Point cloud downsampling based on the transformer features. - Dehghanpour, Alireza; Sharifi, Zahra; Dehyadegari, Masoud (Vis. Comput., 2025)

Genetic Cache: A Machine Learning Approach to Designing DRAM Cache Controllers in HBM Systems. - Amouzegar, Morteza; Rezaalipour, Morteza; Dehyadegari, Masoud (ACM J. Emerg. Technol. Comput. Syst., 2024)

A power-efficient approximate approach to improve the computational complexity of coding tools in versatile video coding. - Oveisi, Sina Shah; Roodaki, Hoda; Rezaalipour, Morteza; Dehyadegari, Masoud (Multim. Tools Appl., 2024)

Accurate Low-Bit Length Floating-Point Arithmetic with Sorting Numbers. - Dehghanpour, Alireza; Kordestani, Javad Khodamoradi; Dehyadegari, Masoud (Neural Process. Lett., 2023)

Linear-time error calculation for approximate adders. - Rezaalipour, Morteza; Dehyadegari, Masoud (Comput. Electr. Eng., 2021)

Memristive Data Ranking. - Prasad, Ananth Krishna; Rezaalipour, Morteza; Dehyadegari, Masoud; Bojnordi, Mahdi Nazm (2021)

G-Arrays: Geometric Arrays for Efficient Point Cloud Processing. - Roodaki, Hoda; Dehyadegari, Masoud; Bojnordi, Mahdi Nazm (2021)

AxMAP: Making Approximate Adders Aware of Input Patterns. - Rezaalipour, Morteza; Rezaalipour, Mohammad; Dehyadegari, Masoud; Bojnordi, Mahdi Nazm (IEEE Trans. Computers, 2020)

Designing energy-efficient imprecise adders with multi-bit approximation. - Tajasob, Sarvenaz; Rezaalipour, Morteza; Dehyadegari, Masoud (Microelectron. J., 2019)

IDrAx: A tool-chain for designing efficient approximate adders. - Rezaalipour, Morteza; Rezaalipour, Mohammad; Tajasob, Sarvenaz; Dehyadegari, Masoud (Microelectron. J., 2019)

Enhanced graph processing in PIM accelerators with improved queue management. - Mosayebi, Mohammad Amin; Mohammadhassani, Arghavan; Dehyadegari, Masoud (Microelectron. J., 2019)

Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks. - Tajasob, Sarvenaz; Rezaalipour, Morteza; Dehyadegari, Masoud; Bojnordi, Mahdi Nazm (2018)

Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators. - Dehyadegari, Masoud; Marongiu, Andrea; Kakoee, Mohammad Reza; Mohammadi, Siamak; Yazdani, Nasser; Benini, Luca (IEEE Trans. Computers, 2015)

Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip. - Ebrahimi, Masoumeh; Tenhunen, Hannu; Dehyadegari, Masoud (J. Syst. Archit., 2013)

Distributed fair DRAM scheduling in network-on-chips architecture. - Dehyadegari, Masoud; Mohammadi, Siamak; Yazdani, Nasser (J. Syst. Archit., 2013)

A tightly-coupled multi-core cluster with shared-memory HW accelerators. - Dehyadegari, Masoud; Marongiu, Andrea; Kakoee, Mohammad Reza; Benini, Luca; Mohammadi, Siamak; Yazdani, Nasser (2012)

An adaptive fuzzy logic-based routing algorithm for networks-on-chip. - Dehyadegari, Masoud; Daneshtalab, Masoud; Ebrahimi, Masoumeh; Plosila, Juha; Mohammadi, Siamak (2011)

Real-time embedded emotional controller. - Jamali, Mohammad Reza; Deh-Yadegari, Masood; Arami, Arash; Lucas, Caro; Navabi, Zainalabedin (Neural Comput. Appl., 2010)

Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization. - Kamal, Mehdi; Amiri, Neda Kazemian; Kamran, Arezoo; Hoseini, Seyyed Alireza; Dehyadegari, Masoud; Noori, Hamid (2010)

Emotion on FPGA: Model driven approach. - Jamali, Mohammad Reza; Arami, Arash; Deh-Yadegari, Masood; Lucas, Caro; Navabi, Zainalabedin (Expert Syst. Appl., 2009)

A New Protocol Stack Model for Network on Chip. - Deh-Yadegari, Masood; Nickray, Mohsen; Afzali-Kusha, Ali; Navabi, Zainalabedin (2006)

Power and delay optimization for network on chip. - Nickray, Mohsen; Dehyadegari, Masoud; Afzali-Kusha, Ali (2005)