Point cloud downsampling based on the transformer features - Alireza Dehghanpour; Zahra Sharifi; Masoud Dehyadegari (Vis. Comput., 2025)

Genetic Cache: A Machine Learning Approach to Designing DRAM Cache Controllers in HBM Systems - Morteza Amouzegar; Morteza Rezaalipour; Masoud Dehyadegari (ACM J. Emerg. Technol. Comput. Syst., 2024)

A power-efficient approximate approach to improve the computational complexity of coding tools in versatile video coding - Sina Shah Oveisi; Hoda Roodaki; Morteza Rezaalipour; Masoud Dehyadegari (Multim. Tools Appl., 2024)

Accurate Low-Bit Length Floating-Point Arithmetic with Sorting Numbers - Alireza Dehghanpour; Javad Khodamoradi Kordestani; Masoud Dehyadegari (Neural Process. Lett., 2023)

Linear-time error calculation for approximate adders - Morteza Rezaalipour; Masoud Dehyadegari (Comput. Electr. Eng., 2021)

Memristive Data Ranking - Ananth Krishna Prasad; Morteza Rezaalipour; Masoud Dehyadegari; Mahdi Nazm Bojnordi (IEEE International Symposium on High-Performance Computer Architecture, HPCA 2021, Seoul, South Korea, February 27 - March 3, 2021, 2021)

G-Arrays: Geometric Arrays for Efficient Point Cloud Processing - Hoda Roodaki; Masoud Dehyadegari; Mahdi Nazm Bojnordi (IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP 2021, Toronto, ON, Canada, June 6-11, 2021, 2021)

AxMAP: Making Approximate Adders Aware of Input Patterns - Morteza Rezaalipour; Mohammad Rezaalipour; Masoud Dehyadegari; Mahdi Nazm Bojnordi (IEEE Trans. Computers, 2020)

Designing energy-efficient imprecise adders with multi-bit approximation - Sarvenaz Tajasob; Morteza Rezaalipour; Masoud Dehyadegari (Microelectron. J., 2019)

IDrAx: A tool-chain for designing efficient approximate adders - Morteza Rezaalipour; Mohammad Rezaalipour; Sarvenaz Tajasob; Masoud Dehyadegari (Microelectron. J., 2019)

Enhanced graph processing in PIM accelerators with improved queue management - Mohammad Amin Mosayebi; Arghavan Mohammadhassani; Masoud Dehyadegari (Microelectron. J., 2019)

Designing Efficient Imprecise Adders using Multi-bit Approximate Building Blocks - Sarvenaz Tajasob; Morteza Rezaalipour; Masoud Dehyadegari; Mahdi Nazm Bojnordi (Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2018, Seattle, WA, USA, July 23-25, 2018, 2018)

Architecture Support for Tightly-Coupled Multi-Core Clusters with Shared-Memory HW Accelerators - Masoud Dehyadegari; Andrea Marongiu; Mohammad Reza Kakoee; Siamak Mohammadi; Nasser Yazdani; Luca Benini (IEEE Trans. Computers, 2015)

Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip - Masoumeh Ebrahimi; Hannu Tenhunen; Masoud Dehyadegari (J. Syst. Archit., 2013)

Distributed fair DRAM scheduling in network-on-chips architecture - Masoud Dehyadegari; Siamak Mohammadi; Nasser Yazdani (J. Syst. Archit., 2013)

A tightly-coupled multi-core cluster with shared-memory HW accelerators - Masoud Dehyadegari; Andrea Marongiu; Mohammad Reza Kakoee; Luca Benini; Siamak Mohammadi; Nasser Yazdani (2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XII, Samos, Greece, July 16-19, 2012, 2012)

An adaptive fuzzy logic-based routing algorithm for networks-on-chip - Masoud Dehyadegari; Masoud Daneshtalab; Masoumeh Ebrahimi; Juha Plosila; Siamak Mohammadi (2011 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2011, San Diego, California, USA, June 6-9, 2011, 2011)

Real-time embedded emotional controller - Mohammad Reza Jamali; Masood Deh-Yadegari; Arash Arami; Caro Lucas; Zainalabedin Navabi (Neural Comput. Appl., 2010)

Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization - Mehdi Kamal; Neda Kazemian Amiri; Arezoo Kamran; Seyyed Alireza Hoseini; Masoud Dehyadegari; Hamid Noori (21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010, 2010)

Emotion on FPGA: Model driven approach - Mohammad Reza Jamali; Arash Arami; Masood Deh-Yadegari; Caro Lucas; Zainalabedin Navabi (Expert Syst. Appl., 2009)

A New Protocol Stack Model for Network on Chip - Masood Deh-Yadegari; Mohsen Nickray; Ali Afzali-Kusha; Zainalabedin Navabi (2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, 2006)

Power and delay optimization for network on chip - Mohsen Nickray; Masoud Dehyadegari; Ali Afzali-Kusha (Proceedings of the 2005 European Conference on Circuit Theory and Design, ECCTD 2005, Cork, Ireland, August 29th - September 1st 2005, 2005)