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ORCIDBob Rau
Person information
- affiliation: Hewlett-Packard Labs, Palo Alto, CA, USA
- affiliation: ESL Inc., San Jose, CA, USA
- affiliation: Cydrome Inc., Los Gatos, CA, USA
- affiliation: Colorado State University, Computer Science Department, Fort Collins, CO, USA
- affiliation: University of Illinois at Urbana-Champaign, Coordinated Science Laboratory, IL, USA
- affiliation (PhD): Stanford University, CA, USA
- award (2002): Eckert-Mauchly Award
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2000 – 2009
- 2002
[j18]Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman:
PICO: Automatically Designing Custom Computers. Computer 35(9): 39-47 (2002)- [j17]Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien
:
Constructing and exploiting linear schedules with prescribed parallelism. ACM Trans. Design Autom. Electr. Syst. 7(1): 159-172 (2002) - [j16]Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman:
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. J. VLSI Signal Process. 31(2): 127-142 (2002) - [e2]Erik R. Altman, Kemal Ebcioglu, Scott A. Mahlke, B. Ramakrishna Rau, Sanjay J. Patel:
Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002. ACM/IEEE Computer Society 2002, ISBN 0-7695-1859-1 [contents] - 2001
- [j15]B. Ramakrishna Rau, Michael S. Schlansker:
Embedded Computer Architecture and Automation. Computer 34(4): 75-83 (2001) - [j14]Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau:
Compiling for EPIC architectures. Proc. IEEE 89(11): 1676-1693 (2001) - 2000
- [j13]Michael S. Schlansker, B. Ramakrishna Rau:
EPIC: Explicititly Parallel Instruction Computing. Computer 33(2): 37-45 (2000) - [j12]Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau:
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. ACM Trans. Design Autom. Electr. Syst. 5(4): 752-773 (2000) - [c27]Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider:
High-Level Synthesis of Nonprogrammable Hardware Accelerators. ASAP 2000: 113- - [c26]Santosh G. Abraham, B. Ramakrishna Rau:
Efficient design space exploration in PICO. CASES 2000: 71-79 - [c25]B. Ramakrishna Rau:
The era of embedded computing. CASES 2000: 119 - [c24]B. Ramakrishna Rau, Michael S. Schlansker:
Embedded Computing: New Directions in Architecture and Automation. HiPC 2000: 225-244 - [c23]Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien:
A Constructive Solution to the Juggling Problem in Processor Array Synthesis. IPDPS 2000: 815-822
1990 – 1999
- 1999
- [j11]B. Ramakrishna Rau, Vinod Kathail, Shail Aditya:
Machine-Description Driven Compilers for EPIC and VLIW Processors. Des. Autom. Embed. Syst. 4(2-3): 71-118 (1999) - [c22]Shail Aditya, B. Ramakrishna Rau, Vinod Kathail:
Automatic Architectural Synthesis of VLIW and EPIC Processors. ISSS 1999: 107-113 - 1998
- [j10]John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau:
Optimization of Machine Descriptions for Efficient Use. Int. J. Parallel Program. 26(4): 417-447 (1998) - 1997
- [j9]Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau:
Region-based compilation: Introduction, motivation, and initial experience. Int. J. Parallel Program. 25(2): 113-146 (1997) - 1996
- [j8]B. Ramakrishna Rau:
Iterative Modulo Scheduling. Int. J. Parallel Program. 24(1): 3-65 (1996) - [c21]Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker:
Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. MICRO 1996: 58-67 - [c20]John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau:
Optimization of Machine Descriptions for Efficient Use. MICRO 1996: 349-358 - 1995
- [c19]Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau:
Region-based compilation: an introduction and motivation. MICRO 1995: 158-168 - 1994
- [c18]B. Ramakrishna Rau:
Iterative modulo scheduling: an algorithm for software pipelining loops. MICRO 1994: 63-74 - 1993
- [j7]Joseph A. Fisher, B. Ramakrishna Rau:
Guest editors' introduction. J. Supercomput. 7(1-2): 7 (1993) - [j6]B. Ramakrishna Rau, Joseph A. Fisher:
Instruction-level parallel processing: History, overview, and perspective. J. Supercomput. 7(1-2): 9-50 (1993) - [j5]Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors. ACM Trans. Comput. Syst. 11(4): 376-408 (1993) - [c17]B. Ramakrishna Rau:
Dynamically scheduled VLIW processors. MICRO 1993: 80-92 - [c16]Santosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. Ramakrishna Rau, Rajiv Gupta:
Predictability of load/store instruction latencies. MICRO 1993: 139-152 - [c15]Nancy J. Warter, Scott A. Mahlke, Wen-mei W. Hwu, B. Ramakrishna Rau:
Reverse If-Conversion. PLDI 1993: 290-299 - 1992
- [c14]Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors. ASPLOS 1992: 238-247 - [c13]B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai:
Code generation schema for modulo scheduled loops. MICRO 1992: 158-169 - [c12]B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker:
Register Allocation for Software Pipelined Loops. PLDI 1992: 283-299 - 1991
- [c11]B. Ramakrishna Rau:
Pseudo-Randomly Interleaved Memory. ISCA 1991: 74-83 - [c10]B. Ramakrishna Rau:
Data Flow and Dependence Analysis for Instruction Level Parallelism. LCPC 1991: 236-250 - [e1]David A. Patterson, Bob Rau:
ASPLOS-IV Proceedings - Forth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, USA, April 8-11, 1991. ACM Press 1991, ISBN 0-89791-380-9 [contents]
1980 – 1989
- 1989
- [j4]B. Ramakrishna Rau, David W. L. Yen, Wei C. Yen, Ross A. Towle:
The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs. Computer 22(1): 12-35 (1989) - [j3]Peter Y.-T. Hsu, B. Ramakrishna Rau, K. J. M. Moriarty:
Appucations Development On the Very Long Instruction Word Cydra-5. Int. J. High Perform. Comput. Appl. 3(3): 91-98 (1989) - [c9]B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen:
The Cydram 5 Stride-Insensitive Memory System. ICPP (1) 1989: 242-246 - 1988
- [c8]B. Ramakrishna Rau:
Cydra 5 Directed Dataflow Architecture. COMPCON 1988: 106-113 - 1982
- [c7]Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker:
Systematically derived instruction sets for high-level language support. ACM Southeast Regional Conference 1982: 73-84 - [c6]B. Ramakrishna Rau, Christopher D. Glaeser, E. M. Greenawalt:
Architectural Support for the Efficient Generation of Code for Horizontal Architectures. ASPLOS 1982: 96-99 - [c5]B. Ramakrishna Rau, Christopher D. Glaeser, Raymond L. Picard:
Efficient code generation for horizontal architectures: Compiler techniques and architectural support. ISCA 1982: 131-139 - 1981
- [c4]B. Ramakrishna Rau, Christopher D. Glaeser:
Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. MICRO 1981: 183-198
1970 – 1979
- 1979
- [j2]B. Ramakrishna Rau:
Program Behavior and the Performance of Interleaved Memories. IEEE Trans. Computers 28(3): 191-199 (1979) - [j1]B. Ramakrishna Rau:
Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System. IEEE Trans. Computers 28(9): 678-681 (1979) - 1978
- [c3]B. Ramakrishna Rau:
Levels of representation of programs and the architecture of universal host machines. MICRO 1978: 67-79 - 1977
- [c2]B. Ramakrishna Rau, George E. Rossman:
The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units. ISCA 1977: 80-89 - 1976
- [c1]B. Ramakrishna Rau:
A new philosophy for interconnection on multilayer boards. DAC 1976: 225-231
Coauthor Index
aka: Michael S. Schlansker
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