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ORCIDShuji Tsukiyama
- > Home > Persons > Shuji Tsukiyama
Publications
- 2011
[c21]Shohei Asakawa, Shuji Tsukiyama, Isao Shirakawa, Shuji Nishi, Tadashi Takeda, Tomoyuki Nagai, Yasushi Kubota:
An automatic layout method for timing pulse generator of small LCD driver. ECCTD 2011: 697-700- 2007
- [j11]Masanori Hashimoto
, Takahito Ijichi, Shingo Takahashi, Shuji Tsukiyama, Isao Shirakawa:
Transistor Sizing of LCD Driver Circuit for Technology Migration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2712-2717 (2007) - 2006
- [j9]Shingo Takahashi, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa:
A Sampling Switch Design Procedure for Active Matrix Liquid Crystal Displays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3538-3545 (2006) - 2005
- [c13]Shingo Takahashi, Akira Taji, Shuji Tsukiyama, Masanori Hashimoto, Isao Shirakawa:
A design scheme for sampling switch in active matrix LCD. ECCTD 2005: 31-34 - [c12]Yoshihiro Uchida, Sadahiro Tani, Masanori Hashimoto, Shuji Tsukiyama, Isao Shirakawa:
Interconnect capacitance extraction for system LCD circuits. ACM Great Lakes Symposium on VLSI 2005: 160-163 - 2003
- [j8]Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai:
Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 2923-2932 (2003) - 2002
- [c10]Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai:
Parasitic capacitance modeling for multilevel interconnects. APCCAS (1) 2002: 59-64 - 2001
- [c8]Makoto Furuie, Takao Onoye, Shuji Tsukiyama, Isao Shirakawa:
Two-dimensional array layout for NMOS 4-phase dynamic logic. ICECS 2001: 589-592 - 1993
- [p1]Shuji Tsukiyama, Keiichi Koike, Isao Shirakawa:
An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan. Algorithmic Aspects of VLSI Layout 1993: 321-335 - 1992
- [c3]Takashi Shimamoto, Hidetaka Hane, Isao Shirakawa, Shuji Tsukiyama, Shoji Shinoda, Nobuyasu Yui, Nobuyuki Nishiguchi:
A distributed routing system for multilayer SOG. EURO-DAC 1992: 298-303 - 1991
- [j6]Katsunori Tani, Shuji Tsukiyama, Shoji Shinoda, Isao Shirakawa:
On area-efficient drawings of rectangular duals for VLSI floor-plan. Math. Program. 52: 29-43 (1991) - 1983
- [j5]Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa:
On the Layering Problem of Multilayer PWB Wiring. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(1): 30-38 (1983) - [j4]Shuji Tsukiyama, Ikuo Harada, Masahiro Fukui, Isao Shirakawa:
A New Global Router for Gate Array LSIsi. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(4): 313-321 (1983) - 1981
- [c2]Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa:
On the layering problem of multilayer PWB wiring. DAC 1981: 738-745 - 1980
- [j2]Shuji Tsukiyama, Isao Shirakawa, Hiroshi Ozaki, Hiromu Ariyoshi:
An Algorithm to Enumerate All Cutsets of a Graph in Linear Time per Cutset. J. ACM 27(4): 619-632 (1980) - [c1]Shuji Tsukiyama, Ernest S. Kuh, Isao Shirakawa:
On the layering problem of multilayer PWB wiring. Graph Theory and Algorithms 1980: 20-37 - 1977
- [j1]Shuji Tsukiyama, Mikio Ide, Hiromu Ariyoshi, Isao Shirakawa:
A New Algorithm for Generating All the Maximal Independent Sets. SIAM J. Comput. 6(3): 505-517 (1977)
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