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ORCIDZule Xu
Publications
- 2024
[j17]Masaru Osada
, Zule Xu, Zunsong Yang, Tetsuya Iizuka:
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. IEEE J. Solid State Circuits 59(7): 2171-2184 (2024)- 2022
- [j13]Masaru Osada, Zule Xu, Ryoya Shibata, Tetsuya Iizuka:
Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 5072-5084 (2022) - [c14]Masaru Osada, Zule Xu, Tetsuya Iizuka:
An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. ESSCIRC 2022: 245-248 - [c13]Ryoya Shibata, Zule Xu, Yasushi Hotta, Hitoshi Tabata, Tetsuya Iizuka:
A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal. ISCAS 2022: 3224-3228 - [c12]Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka:
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. VLSI Technology and Circuits 2022: 10-11 - 2021
- [j12]Zule Xu, Naoki Ojima, Shuowei Li, Tetsuya Iizuka:
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2153-2162 (2021) - [c10]Zule Xu, Masaru Osada, Tetsuya Iizuka:
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. VLSI Circuits 2021: 1-2 - 2020
- [c9]Masaru Osada, Zule Xu, Tetsuya Iizuka:
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. VLSI Circuits 2020: 1-2 - 2019
- [j11]Wang Jing, Tetsuya Iizuka, Zule Xu, Toru Nakura:
A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. IEICE Electron. Express 16(19): 20190546 (2019) - [c7]Naoki Ojima, Zule Xu, Tetsuya Iizuka:
A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS. NEWCAS 2019: 1-4
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