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ORCIDXinmiao Zhang 0001
Person information
- affiliation: Ohio State University, Electrical and Computer Engineering Department, Columbus, OH, USA
- affiliation (former): Western Digital Corporation, Milpitas, CA, USA
- affiliation (former): SanDisk Corporation, Milpitas, CA, USA
- affiliation (former): Case Western Reserve University, Cleveland, OH, USA
- affiliation (PhD 2005): University of Minnesota Twin Cities, MN, USA
Other persons with the same name
- Xinmiao Zhang 0002 — Wuhan University, School of Electronic Information, China
- Xinmiao Zhang 0003 — North China Electric Power University, College of Energy Power and Mechanical Engineering, Beijing, China
- Xinmiao Zhang 0004
![[0000-0002-5178-324X]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-5178-324X")
— Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China (and 2 more) - Xinmiao Zhang 0005 — Shanghai Jiao Tong University, School of Biomedical Engineering, China
- Xinmiao Zhang 0006 — Shandong Normal University, School of Mathematics and Statistics, Jinan, China
- Xinmiao Zhang 0007 — Tsinghua University, School of Social Sciences, Department of Psychology, Beijing, China
- Xinmiao Zhang 0008 — National University of Defense Technology, College of Intelligence Science and Technology, Changsha, China
- Xinmiao Zhang 0009 — Northeastern University, College of Information Science and Engineering, Shenyang, China
- Xinmiao Zhang 0010 — Ministry of Natural Resources, First Institute of Oceanography, Qingdao, China
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2020 – today
- 2024
[j65]Yok Jye Tang, Xinmiao Zhang:
Modified Extended Integrated Interleaved Codes. IEEE Commun. Lett. 28(5): 989-993 (2024)- [j64]Xinmiao Zhang:
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2024. IEEE Trans. Circuits Syst. I Regul. Pap. 71(11): 4899 (2024) - [j63]Xinmiao Zhang:
Guest Editorial Special Issue on the International Symposium on Circuits and Systems - ISCAS 2024. IEEE Trans. Circuits Syst. I Regul. Pap. 71(12): 5375 (2024) - [j62]Yok Jye Tang, Xinmiao Zhang:
Generalized Integrated Interleaved Codes for High-Density DRAMs. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 410-414 (2024) - [j61]Sajjad Akherati, Xinmiao Zhang:
Low-Complexity Ciphertext Multiplication for CKKS Homomorphic Encryption. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1396-1400 (2024) - [j60]Jiafeng Xie, Wenfeng Zhao, Hanho Lee, Debapriya Basu Roy, Xinmiao Zhang:
Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1670-1676 (2024) - [j59]Yok Jye Tang, Xinmiao Zhang:
Low-Complexity Parallel Chien Search Architecture Based on Vandermonde Matrix Decomposition. IEEE Trans. Very Large Scale Integr. Syst. 32(9): 1744-1748 (2024) - [c68]Sajjad Akherati, Jiaxuan Cai, Xinmiao Zhang:
Low-Complexity Integer Divider Architecture for Homomorphic Encryption. SiPS 2024: 131-135 - [c67]Sajjad Akherati, Xinmiao Zhang:
Improved Ciphertext Multiplication for RNS-CKKS Homomorphic Encryption. SiPS 2024: 136-140 - [c66]Jiaxuan Cai, Xinmiao Zhang:
Low-Latency Parallel Row-Layered Min-sum MDPC Decoder for McEliece Cryptosystem. SiPS 2024: 147-152 - [i9]Sajjad Akherati, Jiaxuan Cai, Xinmiao Zhang:
Low-Complexity Integer Divider Architecture for Homomorphic Encryption. CoRR abs/2401.11064 (2024) - [i8]Jiaxuan Cai, Xinmiao Zhang:
Highly Efficient Parallel Row-Layered Min-Sum MDPC Decoder for McEliece Cryptosystem. CoRR abs/2407.12695 (2024) - [i7]Sajjad Akherati, Xinmiao Zhang:
Efficient Homomorphically Encrypted Convolutional Neural Network Without Rotation. CoRR abs/2409.05205 (2024) - [i6]Sajjad Akherati, Yok Jye Tang, Xinmiao Zhang:
Three-Input Ciphertext Multiplication for Homomorphic Encryption. CoRR abs/2410.13545 (2024) - 2023
- [j58]Yok Jye Tang, Xinmiao Zhang:
Fast and Low-Complexity Soft-Decision Generalized Integrated Interleaved Decoder. IEEE J. Sel. Areas Inf. Theory 4: 174-189 (2023) - [j57]Tuvi Etzion, Paul H. Siegel, Han Mao Kiah, Hessam Mahdavifar, Farzad Parvaresh, Moshe Schwartz, Ido Tal, Eitan Yaakobi, Xinmiao Zhang:
Dimensions of Channel Coding: From Theory to Algorithms to Applications. IEEE J. Sel. Areas Inf. Theory 4: v-xiii (2023) - [j56]Weihang Tan, Antian Wang, Xinmiao Zhang, Yingjie Lao, Keshab K. Parhi:
High-Speed VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography. IEEE Trans. Computers 72(9): 2454-2466 (2023) - [j55]Jingbo Zhou, Xinmiao Zhang:
Algorithmic Obfuscation for LDPC Decoders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 371-383 (2023) - [j54]Jingbo Zhou, Xinmiao Zhang:
Joint Protection Scheme for Deep Neural Network Hardware Accelerators and Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4518-4527 (2023) - [j53]Jiaxuan Cai, Xinmiao Zhang:
Low-Complexity Parallel Min-Sum Medium-Density Parity-Check Decoder for McEliece Cryptosystem. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 5328-5338 (2023) - [j52]Xinmiao Zhang, Zhenshan Xie:
Sparsity-Aware Medium-Density Parity-Check Decoder for McEliece Cryptosystems. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3343-3347 (2023) - 2022
- [j51]Oscar Ferraz, Srinivasan Subramaniyan, Ramesh Chinthalaa, João Andrade, Joseph R. Cavallaro, Soumitra Kumar Nandy, Vítor Silva, Xinmiao Zhang, Madhura Purnaprajna, Gabriel Falcão:
A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA, and GPU Architectures. IEEE Commun. Surv. Tutorials 24(1): 524-556 (2022) - [j50]Yok Jye Tang, Xinmiao Zhang:
Fast En/Decoding of Reed-Solomon Codes for Failure Recovery. IEEE Trans. Computers 71(3): 724-735 (2022) - [j49]Yok Jye Tang, Xinmiao Zhang:
Low-Complexity Resource-Shareable Parallel Generalized Integrated Interleaved Encoder. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 694-706 (2022) - [j48]Zhenshan Xie, Xinmiao Zhang:
Efficient Sub-Codeword Key Equation Solver for Generalized Integrated Interleaved BCH Decoder. IEEE Trans. Circuits Syst. II Express Briefs 69(1): 85-89 (2022) - [j47]Zhenshan Xie, Yok Jye Tang, Xinmiao Zhang:
Low-Latency Nested Decoding for Short Generalized Integrated Interleaved BCH Codes. IEEE Trans. Very Large Scale Integr. Syst. 30(10): 1563-1567 (2022) - [j46]Xinmiao Zhang, Zheang Huai, Keshab K. Parhi:
Polynomial Multiplication Architecture with Integrated Modular Reduction for R-LWE Cryptosystems. J. Signal Process. Syst. 94(8): 799-809 (2022) - [j45]Zheang Huai, Jingbo Zhou, Xinmiao Zhang:
Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime. J. Signal Process. Syst. 94(10): 1067-1082 (2022) - [c65]Zhenshan Xie, Xinmiao Zhang:
Improved Miscorrection Detection for Generalized Integrated Interleaved BCH Codes. ICC 2022: 3442-3447 - [c64]Jingbo Zhou, Elsayed Elgendy, Eslam Yahya Tawfik, Xinmiao Zhang:
Low-Complexity AES Architectures Resilient to Power Analysis Attacks. ISCAS 2022: 165-169 - [c63]Xinmiao Zhang:
Efficient Check Node Processing for Min-Max NB-LDPC Decoding over Lower-Order Finite Fields. ISCAS 2022: 2062-2066 - [c62]Zhenshan Xie, Xinmiao Zhang:
Efficient Nested Key Equation Solver for Short Generalized Integrated Interleaved BCH Codes. ISCAS 2022: 2067-2071 - [c61]Yok Jye Tang, Xinmiao Zhang:
Efficient Reconfigurable Vandermonde Matrix Inverter for Erasure-Correcting Generalized Integrated Interleaved Decoding. SiPS 2022: 1-6 - [i5]Jingbo Zhou, Xinmiao Zhang:
Joint Protection Scheme for Deep Neural Network Hardware Accelerators and Models. CoRR abs/2210.03249 (2022) - 2021
- [j44]Zhenshan Xie, Xinmiao Zhang:
Miscorrection Mitigation for Generalized Integrated Interleaved BCH Codes. IEEE Commun. Lett. 25(7): 2118-2122 (2021) - [j43]Deepu John, Yongfu Li, Xinmiao Zhang:
Special Section on Edge AI and Accelerators. IEEE Open J. Circuits Syst. 2: 128-130 (2021) - [j42]Zhenshan Xie, Xinmiao Zhang:
Fast Nested Key Equation Solvers for Generalized Integrated Interleaved Decoder. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 483-495 (2021) - [j41]Jingbo Zhou, Xinmiao Zhang:
Generalized SAT-Attack-Resistant Logic Locking. IEEE Trans. Inf. Forensics Secur. 16: 2581-2592 (2021) - [c60]Weihang Tan, Antian Wang, Yingjie Lao, Xinmiao Zhang, Keshab K. Parhi:
Pipelined High-Throughput NTT Architecture for Lattice-Based Cryptography. AsianHOST 2021: 1-4 - [c59]Xinmiao Zhang, Keshab K. Parhi:
Reduced-Complexity Modular Polynomial Multiplication for R-LWE Cryptosystems. ICASSP 2021: 7853-7857 - [c58]Zhenshan Xie, Xinmiao Zhang:
Scaled Fast Nested Key Equation Solver for Generalized Integrated Interleaved BCH Decoders. ICASSP 2021: 7883-7887 - [c57]Xinmiao Zhang, Yok Jye Tang:
Low-Complexity Parallel Cyclic Redundancy Check. ISCAS 2021: 1-5 - [c56]Jingbo Zhou, Xinmiao Zhang:
A Low-Complexity Flexible Logic-Locking Scheme Resisting Removal Attacks. MWSCAS 2021: 869-873 - [c55]Zheang Huai, Keshab K. Parhi, Xinmiao Zhang:
Efficient Architecture for Long Integer Modular Multiplication over Solinas Prime. SiPS 2021: 146-151 - [c54]Yok Jye Tang, Xinmiao Zhang:
An Efficient Parallel Architecture for Resource-Shareable Reed-Solomon Encoder. SiPS 2021: 152-157 - [i4]Jingbo Zhou, Xinmiao Zhang:
Algorithmic Obfuscation for LDPC Decoders. CoRR abs/2104.03814 (2021) - [i3]Weihang Tan, Antian Wang, Yingjie Lao, Xinmiao Zhang, Keshab K. Parhi:
Low-Latency VLSI Architectures for Modular Polynomial Multiplication via Fast Filtering and Applications to Lattice-Based Cryptography. CoRR abs/2110.12127 (2021) - 2020
- [j40]Xinmiao Zhang:
VLSI Architectures for Reed-Solomon Codes: Classic, Nested, Coupled, and Beyond. IEEE Open J. Circuits Syst. 1: 157-169 (2020) - [j39]Xinmiao Zhang, Zhenshan Xie:
Efficient VLSI Architectures for Coupled-Layered Regenerating Codes. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 1869-1873 (2020) - [j38]Zhenshan Xie, Xinmiao Zhang:
Scaled Nested Key Equation Solver for Generalized Integrated Interleaved Decoder. IEEE Trans. Circuits Syst. 67-II(11): 2457-2461 (2020) - [j37]Zhenshan Xie, Xinmiao Zhang:
Reduced-Complexity Key Equation Solvers for Generalized Integrated Interleaved BCH Decoders. IEEE Trans. Circuits Syst. 67-I(12): 5520-5529 (2020) - [c53]Xinmiao Zhang:
High-Speed and Low-Complexity Parallel Long BCH Encoder. ISCAS 2020: 1-5 - [c52]Xinmiao Zhang, Zhenshan Xie:
Efficient Architectures for Generalized Integrated Interleaved Decoder. ISCAS 2020: 1 - [c51]Jingbo Zhou, Xinmiao Zhang:
A New Logic-Locking Scheme Resilient to Gate Removal Attack. ISCAS 2020: 1-5 - [c50]Xinmiao Zhang:
Efficient Nested Key Equation Solver Architectures for Generalized Integrated Interleaved Codes. ITA 2020: 1-6 - [c49]Yok Jye Tang, Xinmiao Zhang:
Low-Complexity Architectures for Parallel Long BCH Encoders. SiPS 2020: 1-6
2010 – 2019
- 2019
- [j36]Xinmiao Zhang, Zhenshan Xie:
Relaxing the Constraints on Locally Recoverable Erasure Codes by Finite Field Element Variation. IEEE Commun. Lett. 23(10): 1680-1683 (2019) - [j35]Xinmiao Zhang, Yingjie Lao:
On the Construction of Composite Finite Fields for Hardware Obfuscation. IEEE Trans. Computers 68(9): 1353-1364 (2019) - [j34]Xinmiao Zhang:
A Low-Power Parallel Architecture for Linear Feedback Shift Registers. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 412-416 (2019) - [j33]Xinmiao Zhang, Zhenshan Xie:
Efficient Architectures for Generalized Integrated Interleaved Decoder. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 4018-4031 (2019) - [c48]Xinmiao Zhang:
Systematic Encoder of Generalized Three-Layer Integrated Interleaved Codes. ICC 2019: 1-6 - [c47]Ankur A Sharma, Xinmiao Zhang, Yingjie Lao:
Hardware Obfuscation Through Reconfiguration Finite Field Arithmetic Units. ISCAS 2019: 1-5 - [c46]Xinmiao Zhang, Phillip Shvartsman, Jingbo Zhou, Eslam Yahya Tawfik:
Hardware Obfuscation of AES through Finite Field Construction Variation. ISCAS 2019: 1-5 - [c45]Xinmiao Zhang, Yok Jye Tang:
Reducing Parallel Linear Feedback Shift Register Complexity Through Input Tap Modification. ISCAS 2019: 1-5 - [c44]Xinmiao Zhang:
Decoding of Generalized Three-Layer Integrated Interleaved Codes. ISIT 2019: 2424-2428 - [c43]Phillip Shvartsman, Xinmiao Zhang:
Side Channel Attack Resistant AES Design Based on Finite Field Construction Variation. SiPS 2019: 67-72 - [i2]Jingbo Zhou, Xinmiao Zhang:
Generalized SAT-Attack-Resistant Logic Locking. CoRR abs/1910.12142 (2019) - 2018
- [j32]Xinmiao Zhang:
Generalized Three-Layer Integrated Interleaved Codes. IEEE Commun. Lett. 22(3): 442-445 (2018) - [c42]Xinmiao Zhang, Alexander Bazarsky:
Perfect Column-Layered Two-Bit Message-Passing LDPC Decoder and Architectures. ISCAS 2018: 1-5 - [c41]Xinmiao Zhang, Michael O'Sullivan:
Ultra-Compressed Three-Error-Correcting BCH Decoder. ISCAS 2018: 1-5 - 2017
- [j31]Xinmiao Zhang:
Modified Generalized Integrated Interleaved Codes for Local Erasure Recovery. IEEE Commun. Lett. 21(6): 1241-1244 (2017) - [j30]Xinmiao Zhang, Ying Tai:
Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Nonbinary LDPC Codes Over Subfields. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1342-1351 (2017) - 2016
- [j29]Xinmiao Zhang, Steven Sprouse, Ishai Ilani:
A Flexible and Low-Complexity Local Erasure Recovery Scheme. IEEE Commun. Lett. 20(11): 2129-2132 (2016) - [c40]Xinmiao Zhang, Itai Dror, Sanel Alterman:
Low-power partial-parallel Chien search architecture with polynomial degree reduction. ISCAS 2016: 2459-2462 - 2015
- [j28]Xinmiao Zhang:
Low-Complexity Modified Trellis-Based Min-Max Non- Binary LDPC Decoders. J. Commun. 10(11): 836-842 (2015) - [c39]Xinmiao Zhang:
Modified trellis-based Min-max decoder for non-binary LDPC codes. ICNC 2015: 613-617 - 2014
- [j27]Fang Cai, Xinmiao Zhang, David Declercq, Shiva Kumar Planjery, Bane Vasic:
Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1366-1375 (2014) - [j26]Fang Cai, Xinmiao Zhang:
Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation. J. Signal Process. Syst. 76(2): 211-222 (2014) - [c38]Xinmiao Zhang, Ying Tai:
High-speed multi-block-row layered decoding for Quasi-cyclic LDPC codes. GlobalSIP 2014: 11-14 - [c37]Xinmiao Zhang:
Interpolation-based Chase BCH decoder. ITA 2014: 1-5 - 2013
- [j25]Xinmiao Zhang:
An Efficient Interpolation-Based Chase BCH Decoder. IEEE Trans. Circuits Syst. II Express Briefs 60-II(4): 212-216 (2013) - [j24]Xinmiao Zhang, Yu Zheng:
Generalized Backward Interpolation for Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Commun. 61(1): 13-23 (2013) - [j23]Fang Cai, Xinmiao Zhang:
Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2010-2023 (2013) - [c36]Xinmiao Zhang, Fang Cai, M. P. Anantram:
Low-energy and low-latency error-correction for phase change memory. ISCAS 2013: 1236-1239 - [c35]Fang Cai, Xinmiao Zhang, David Declercq, Bane Vasic, Dung Viet Nguyen, Shiva Kumar Planjery:
Low-complexity finite alphabet iterative decoders for LDPC codes. ISCAS 2013: 1332-1335 - [c34]Wei Zhang, Jing Wang, Xinmiao Zhang:
Low-power design of Reed-Solomon encoders. ISCAS 2013: 1560-1563 - [c33]Xinmiao Zhang, Richard Shi, James A. Ritcey:
Reducing the latency of Lee-O'Sullivan interpolation through modified initialization. ITA 2013: 1-5 - 2012
- [j22]Xinmiao Zhang, Jiangli Zhu, Wei Zhang:
Efficient Reencoder Architectures for Algebraic Soft-Decision Reed-Solomon Decoding. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 163-167 (2012) - [j21]Xinmiao Zhang, Yu Zheng:
Systematically Re-encoded Algebraic Soft-Decision Reed-Solomon Decoder. IEEE Trans. Circuits Syst. II Express Briefs 59-II(6): 376-380 (2012) - [j20]Xinmiao Zhang, Zhongfeng Wang:
A Low-Complexity Three-Error-Correcting BCH Decoder for Optical Transport Network. IEEE Trans. Circuits Syst. II Express Briefs 59-II(10): 663-667 (2012) - [j19]Xinmiao Zhang, Yingquan Wu, Jiangli Zhu, Yu Zheng:
Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding. IEEE Trans. Very Large Scale Integr. Syst. 20(7): 1318-1322 (2012) - [j18]Xinmiao Zhang, Fang Cai, Shu Lin:
Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 1938-1950 (2012) - [j17]Xinmiao Zhang, Jiangli Zhu, Wei Zhang:
Modified Low-Complexity Chase Soft-Decision Decoder of Reed-Solomon Codes. J. Signal Process. Syst. 66(1): 3-13 (2012) - [j16]Jiangli Zhu, Xinmiao Zhang:
Efficient Generalized Minimum-distance Decoders of Reed-Solomon Codes. J. Signal Process. Syst. 66(3): 245-257 (2012) - [c32]Wei Zhang, Xinmiao Zhang, Hao Wang:
Increasing the energy efficiency of WSNs using algebraic soft-decision reed-solomon decoders. APCCAS 2012: 49-52 - [c31]Xinmiao Zhang, Yu Zheng, Yingquan Wu:
A Chase-type Koetter-Vardy algorithm for soft-decision Reed-Solomon decoding. ICNC 2012: 466-470 - [c30]Xinmiao Zhang, Jea Hack Lee, Myung Hoon Sunwoo:
Phase recovery for QPSK transmission without using complex multipliers. ICUIMC 2012: 125:1-125:4 - [c29]Xinmiao Zhang, Fang Cai, Richard Shi:
Low-power LDPC decoding based on iteration prediction. ISCAS 2012: 3041-3044 - [c28]Byung Jun Choi, Jae Do Lee, Myung Hoon Sunwoo, Xinmiao Zhang:
Low complexity full parallel Multi-Split LDPC decoder reusing sign wire of row processor. ISOCC 2012: 219-222 - [c27]Xinmiao Zhang, Richard Shi, James A. Ritcey:
On the implementation of modified fuzzy vault for biometric encryption. ITA 2012: 56-61 - [c26]Fang Cai, Xinmiao Zhang:
Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation. SiPS 2012: 137-142 - [i1]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang:
Reduced-Complexity Column-Layered Decoding and Implementation for LDPC Codes. CoRR abs/1204.2577 (2012) - 2011
- [j15]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang:
Reduced-complexity column-layered decoding and implementation for LDPC codes. IET Commun. 5(15): 2177-2186 (2011) - [j14]Somnath Paul, Fang Cai, Xinmiao Zhang, Swarup Bhunia:
Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache. IEEE Trans. Computers 60(1): 20-34 (2011) - [j13]Xinmiao Zhang, Fang Cai:
Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(2): 402-414 (2011) - [j12]Xinmiao Zhang, Fang Cai:
Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 19(7): 1229-1238 (2011) - [c25]Xinmiao Zhang, Fang Cai:
An efficient architecture for iterative soft reliability-based majority-logic non-binary LDPC decoding. ACSCC 2011: 885-888 - [c24]Xinmiao Zhang, Fang Cai:
Low-complexity architectures for reliability-based message-passing non-binary LDPC decoding. ISCAS 2011: 1303-1306 - [c23]Xinmiao Zhang, Yingquan Wu, Jiangli Zhu:
A novel polynomial selection scheme for low-complexity chase algebraic soft-decision reed-solomon decoding. ISCAS 2011: 2689-2692 - [c22]Xinmiao Zhang, Yu Zheng:
Efficient codeword recovery architecture for low-complexity Chase Reed-Solomon decoding. ITA 2011: 510-513 - 2010
- [j11]Xinmiao Zhang, Jiangli Zhu:
High-Throughput Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(3): 581-591 (2010) - [j10]Xinmiao Zhang, Jiangli Zhu:
Algebraic Soft-Decision Decoder Architectures for Long Reed-Solomon Codes. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 787-792 (2010) - [c21]Xinmiao Zhang, Fang Cai:
Reduced-latency scheduling scheme for min-max non-binary LDPC decoding. APCCAS 2010: 414-417 - [c20]Jiangli Zhu, Xinmiao Zhang:
Efficient architecture for generalized minimum-distance decoder of Reed-Solomon codes. ICASSP 2010: 1502-1505 - [c19]Xinmiao Zhang, Fang Cai:
Partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes. ICASSP 2010: 1506-1509 - [c18]Yang Chen, Xinmiao Zhang:
High-speed architecture for image reconstruction based on compressive sensing. ICASSP 2010: 1574-1577 - [c17]Jiangli Zhu, Xinmiao Zhang:
High-speed re-encoder design for algebraic soft-decision Reed-Solomon decoding. ISCAS 2010: 465-468 - [c16]Xinmiao Zhang, Jiangli Zhu:
Hardware complexities of algebraic soft-decision Reed-Solomon decoders and comparisons. ITA 2010: 558-567
2000 – 2009
- 2009
- [j9]Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang:
Backward Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding. IEEE Trans. Very Large Scale Integr. Syst. 17(11): 1602-1615 (2009) - [c15]Jiangli Zhu, Xinmiao Zhang:
Factorization-free Low-complexity Chase Soft-decision Decoding of Reed-Solomon Codes. ISCAS 2009: 2677-2680 - 2008
- [j8]Jiangli Zhu, Xinmiao Zhang:
Efficient VLSI Architecture for Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(10): 3050-3062 (2008) - [c14]Xinmiao Zhang:
VLSi architecture design for algebraic soft-decision Reed-Solomon decoding. ACSCC 2008: 1518-1522 - [c13]Jiangli Zhu, Xinmiao Zhang:
Scalable interpolation architecture for soft-decision Reed-Solomon decoding. APCCAS 2008: 41-44 - [c12]Qingwei Li, Zhongfeng Wang, Xinmiao Zhang, Xingcheng Liu:
Efficient architecture for the Tate pairing in characteristic three. APCCAS 2008: 1111-1115 - [c11]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang, Qingwei Jia:
Efficient decoder design for high-throughput LDPC decoding. APCCAS 2008: 1640-1643 - [c10]Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang:
Combined interpolation architecture for soft-decision decoding of Reed-Solomon codes. ICCD 2008: 526-531 - [c9]Bainan Chen, Xinmiao Zhang:
FPGA implementation of a factorization processor for soft-decision reed-solomon decoding. ISCAS 2008: 944-947 - [c8]Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang:
Novel interpolation architecture for Low-Complexity Chase soft-decision decoding of Reed-Solomon codes. ISCAS 2008: 3078-3081 - [c7]Xinmiao Zhang, Jiangli Zhu:
Efficient interpolration architecture for soft-decision Reed-Solomon decoding by applying slow-down. SiPS 2008: 19-24 - [c6]Bainan Chen, Xinmiao Zhang, Zhongfeng Wang:
Error correction for multi-level NAND flash memory using Reed-Solomon codes. SiPS 2008: 94-99 - 2007
- [j7]Nicolas Sklavos, Máire McLoone, Xinmiao Zhang:
MONET Special Issue on Next Generation Hardware Architectures for Secure Mobile Computing. Mob. Networks Appl. 12(4): 229-230 (2007) - [j6]Xinmiao Zhang:
Further Exploring the Strength of Prediction in the Factorization of Soft-Decision Reed-Solomon Decoding. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 811-820 (2007) - [c5]Xinmiao Zhang, Jiangli Zhu:
Low-complexity Interpolation Architecture for Soft-decision Reed-Solomon Decoding. ISCAS 2007: 1413-1416 - [c4]Jiangli Zhu, Xinmiao Zhang:
Efficient Interpolation Architecture for Soft-Decision Reed-Solomon Decoding. SiPS 2007: 663-668 - 2006
- [j5]Xinmiao Zhang, Keshab K. Parhi:
On the Optimum Constructions of Composite Field for the AES Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1153-1157 (2006) - [j4]Xinmiao Zhang:
Reduced Complexity Interpolation Architecture for Soft-Decision Reed-Solomon Decoding. IEEE Trans. Very Large Scale Integr. Syst. 14(10): 1156-1161 (2006) - [c3]Xinmiao Zhang:
Partial parallel factorization in soft-decision Reed-Solomon decoding. ACM Great Lakes Symposium on VLSI 2006: 272-277 - [c2]Xinmiao Zhang:
High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding. ICCD 2006: 370-375 - 2005
- [j3]Xinmiao Zhang, Keshab K. Parhi:
Fast factorization architecture in soft-decision Reed-Solomon decoding. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 413-426 (2005) - [j2]Xinmiao Zhang, Keshab K. Parhi:
High-Speed Architectures for Parallel Long BCH Encoders. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 872-877 (2005) - 2004
- [j1]Xinmiao Zhang, Keshab K. Parhi:
High-speed VLSI architectures for the AES algorithm. IEEE Trans. Very Large Scale Integr. Syst. 12(9): 957-967 (2004) - [c1]Xinmiao Zhang, Keshab K. Parhi:
High-speed architectures for parallel long BCH encoders. ACM Great Lakes Symposium on VLSI 2004: 1-6
Coauthor Index
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