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ORCIDG. K. Sharma 0001
Person information
- affiliation: ABV-Indian Institute of Information Technology and Management, Gwalior, India
Other persons with the same name
- G. K. Sharma 0002 — Indian Institute of Science, Mechanical Engineering Department, Bangalore, India
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2020 – today
- 2024
[j27]Garima Nain
, Kiran Kumar Pattanaik, Gopal Krishan Sharma, Himanshu Gauttam:
PackMASNet: An information integration approach for quality inspection in industry 5.0. Expert Syst. Appl. 255: 124582 (2024)- [j26]Garima Nain, Kiran Kumar Pattanaik, Gopal Krishan Sharma:
A Novel Semi-Supervised Learning for Industrial Edge Computing Platforms in Quality Prediction. SN Comput. Sci. 5(5): 637 (2024) - [c27]Richa Sharma, G. K. Sharma, Manisha Pattanaik:
Adversarial Label Flipping Attack on Supervised Machine Learning-Based HT Detection Systems. ISCAS 2024: 1-5 - 2023
- [j25]Richa Sharma, G. K. Sharma, Manisha Pattanaik, V. S. S. Prashant:
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model. J. Electron. Test. 39(4): 465-485 (2023) - [j24]Vijaypal Singh Rathor, G. K. Sharma:
A New ATPG and Online Monitoring based Technique for Hardware Trojan Detection. Microprocess. Microsystems 101: 104903 (2023) - [c26]Richa Sharma, G. K. Sharma, Manisha Pattanaik:
Novel Label Flipping Dataset Poisoning Attack Against ML-Based HT Detection Systems. APCCAS 2023: 80-84 - [c25]Garima Nain, K. K. Pattanaik, G. K. Sharma, Himanshu Gauttam, Wattana Viriyasitavat:
A Novel Mechanism for Continual Learning based Predictive Quality Inspection in Smart Manufacturing. TENCON 2023: 606-611 - 2022
- [j23]Richa Sharma, G. K. Sharma, Manisha Pattanaik:
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems. J. Electron. Test. 38(6): 667-682 (2022) - [j22]Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma:
Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations. Microprocess. Microsystems 90: 104498 (2022) - 2021
- [j21]Vijaypal Singh Rathor, Bharat Garg, Mandar Patil, G. K. Sharma:
Security analysis of image CAPTCHA using a mask R-CNN-based attack model. Int. J. Ad Hoc Ubiquitous Comput. 36(4): 238-247 (2021) - [j20]Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma:
READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency. Integr. 76: 1-12 (2021) - [j19]Richa Sharma, Vijaypal Singh Rathor, G. K. Sharma, Manisha Pattanaik:
A new hardware Trojan detection technique using deep convolutional neural network. Integr. 79: 1-11 (2021) - [j18]Vijaypal Singh Rathor, G. K. Sharma:
A Lightweight Robust Logic Locking Technique to Thwart Sensitization and Cone-Based Attacks. IEEE Trans. Emerg. Top. Comput. 9(2): 811-822 (2021) - [j17]Neelam Arya, Manisha Pattanaik, G. K. Sharma:
Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1994-1997 (2021) - [c24]Richa Sharma, G. K. Sharma, Manisha Pattanaik:
A Few Shot Learning based Approach for Hardware Trojan Detection using Deep Siamese CNN. VLSID 2021: 163-168 - 2020
- [j16]Vijaypal Singh Rathor, Bharat Garg, G. K. Sharma:
New lightweight Anti-SAT block design and obfuscation technique to thwart removal attack. Integr. 75: 178-188 (2020) - [j15]Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma:
Bit significance based reconfigurable approximate restoring dividers and square rooters. Microelectron. J. 104: 104861 (2020) - [j14]Vijaypal Singh Rathor, Bharat Garg, G. K. Sharma:
A Novel Low Complexity Logic Encryption Technique for Design-for-Trust. IEEE Trans. Emerg. Top. Comput. 8(3): 688-699 (2020) - [c23]Richa Sharma, Nitya Kritin Valivati, G. K. Sharma, Manisha Pattanaik:
A New Hardware Trojan Detection Technique using Class Weighted XGBoost Classifier. VDAT 2020: 1-6 - [c22]Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma:
Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications. VLSID 2020: 90-95
2010 – 2019
- 2019
- [j13]Bharat Garg, G. K. Sharma:
A process-tolerant low-power adder architecture for image processing applications. Turkish J. Electr. Eng. Comput. Sci. 27(3): 1839-1854 (2019) - [j12]Bharat Garg, Shireesh Kumar Rai, Akash Puranik, G. K. Sharma:
ES-COINA: A novel energy scalable quality-aware color interpolation architecture. Microprocess. Microsystems 67: 8-17 (2019) - [c21]Neelam Arya, Anil Kumar Rajput, Manisha Pattanaik, G. K. Sharma:
Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard. VDAT 2019: 398-412 - 2018
- [j11]Vijaypal Singh Rathor, Bharat Garg, G. K. Sharma:
New Lightweight Architectures for Secure FSM Design to Thwart Fault Injection and Trojan Attacks. J. Electron. Test. 34(6): 697-708 (2018) - [c20]Vijaypal Singh Rathor, Bharat Garg, G. K. Sharma:
An Energy-Efficient Trusted FSM Design Technique to Thwart Fault Injection and Trojan Attacks. VLSID 2018: 73-78 - 2017
- [j10]Bharat Garg, G. K. Sharma:
ACM: An Energy-Efficient Accuracy Configurable Multiplier for Error-Resilient Applications. J. Electron. Test. 33(4): 479-489 (2017) - [j9]Vijaypal Singh Rathor, Bharat Garg, G. K. Sharma:
New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs. J. Electron. Test. 33(5): 657-668 (2017) - 2016
- [j8]Neha K. Nawandar, Bharat Garg, G. K. Sharma:
RICO: A low power repetitive iteration CORDIC for DSP applications in portable devices. J. Syst. Archit. 70: 82-92 (2016) - [j7]Bharat Garg, G. K. Sharma:
A quality-aware Energy-scalable Gaussian Smoothing Filter for image processing applications. Microprocess. Microsystems 45: 1-9 (2016) - [j6]Bharat Garg, Sunil Dutt, G. K. Sharma:
Bit-width-aware constant-delay run-time Accuracy Programmable Adder for error-resilient applications. Microelectron. J. 50: 1-7 (2016) - [c19]Bharat Garg, G. K. Sharma:
Low power signal processing via approximate multiplier for error-resilient applications. ICIIS 2016: 546-551 - [c18]Bharat Garg, G. K. Sharma:
A block matching algorithm for deriving quality-tunable motion estimation architecture. ICIIS 2016: 552-557 - [c17]Bharat Garg, V. N. S. K. Chaitanya Goteti, G. K. Sharma:
A low-cost energy efficient image scaling processor for multimedia applications. VDAT 2016: 1-6 - [c16]Bharat Garg, Sameer Yadav, G. K. Sharma:
An area and performance aware ECG encoder design for wireless healthcare services. VDAT 2016: 1-6 - 2015
- [j5]Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma:
New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET. J. Low Power Electron. 11(1): 49-62 (2015) - [j4]Bharat Garg, G. K. Sharma:
PAID: Process Aware Imprecise DCT Architecture Trading Quality for Energy Efficiency. J. Low Power Electron. 11(2): 121-132 (2015) - [j3]Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma:
A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM. Microelectron. Reliab. 55(8): 1131-1143 (2015) - [c15]Ankur Jaiswal, Bharat Garg, Vikas Kaushal, G. K. Sharma:
SPAA-Aware 2D Gaussian Smoothing Filter Design Using Efficient Approximation Techniques. VLSID 2015: 333-338 - [c14]Vikas Kaushal, Bharat Garg, Ankur Jaiswal, G. K. Sharma:
Energy Aware Computation Driven Approximate DCT Architecture for Image Processing. VLSID 2015: 357-362 - 2014
- [c13]Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma:
NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique. NANOARCH 2014: 122-128 - [c12]Bharat Garg, Nitesh K. Bharadwaj, G. K. Sharma:
Energy scalable approximate DCT architecture trading quality via boundary error-resiliency. SoCC 2014: 306-311 - [c11]Ekta Prajapati, Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma:
Operation-aware assist circuit design for improved write performance of FinFET based SRAM. VDAT 2014: 1-6 - [c10]Nandakishor Yadav, Sunil Dutt, G. K. Sharma:
A New Sensitivity-Driven Process Variation Aware Self-Repairing Low-Power SRAM Design. VLSID 2014: 116-121 - [i2]Vaibhav Jha, Sunny Deol, Mohit Jha, G. K. Sharma:
Energy and Latency Aware Application Mapping Algorithm & Optimization for Homogeneous 3D Network on Chip. CoRR abs/1404.2512 (2014) - [i1]Vaibhav Jha, Mohit Jha, G. K. Sharma:
Estimation of Optimized Energy and Latency Constraints for Task Allocation in 3d Network on Chip. CoRR abs/1405.0109 (2014) - 2013
- [c9]Nandakishor Yadav, Sunil Dutt, Manisha Pattanaik, G. K. Sharma:
Double-gate FinFET process variation aware 10T SRAM cell topology design and analysis. ECCTD 2013: 1-4 - [c8]Rahul Krishnamurthy, G. K. Sharma:
An Area Efficient Wide Range On-Chip Delay Measurement Architecture. VDAT 2013: 49-58 - 2010
- [c7]Prateek Vajpayee, Anurag Srivastava, Sher S. Rajput, G. K. Sharma:
Low voltage regulated cascode current mirrors suitable for sub-1V operation. APCCAS 2010: 584-587 - [c6]Saurabh Agrawal, Dhawal Sant, G. K. Sharma:
An efficient energy- and bandwidth- aware mapping algorithm for regular NoC architecture. NoCArc@MICRO 2010: 51-55
2000 – 2009
- 2009
- [j2]V. P. Singh, Snehashish Chakraverty, R. K. Sharma, G. K. Sharma:
Modeling vibration frequencies of annular plates by regression based neural network. Appl. Soft Comput. 9(1): 439-447 (2009) - 2007
- [j1]Nirved Pandey, G. K. Sharma:
Startup comparison for message passing libraries with DTM on linux clusters. J. Supercomput. 39(1): 59-72 (2007) - 2006
- [c5]Hiren Joshi, S. S. Verma, G. K. Sharma:
Quality Driven Dynamic Low Power Reconfiguration of Handhelds. ARC 2006: 59-64 - 2005
- [c4]Hiren Joshi, S. S. Verma, G. K. Sharma:
Requested-QoS Driven Runtime Reconfiguration of Mobile Devices. FPL 2005: 743-744 - 2003
- [c3]Nirved Pandey, G. K. Sharma:
Equivalent Query Transformer for Semantic Query Optimization in Distributed Computing Environment. Applied Informatics 2003: 529-534 - 2002
- [c2]Seema Bawa, G. K. Sharma:
A Parallel Transitive Closure Computation Algorithm for VLSI Test Generation. PARA 2002: 243-252
1990 – 1999
- 1991
- [c1]Peter Poechmueller, G. K. Sharma, Manfred Glesner:
A CAD tool for designing large, fault-tolerant VLSI arrays. Great Lakes Symposium on VLSI 1991: 132-137
Coauthor Index
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last updated on 2024-10-07 21:15 CEST by the dblp team
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