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Eugenio Villar
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2020 – today
- 2023
- [c60]Héctor Posadas, José Luis Vázquez, Eugenio Villar:
Automatic code generation from UML for data memory optimization in microcontrollers. DCIS 2023: 1-6 - [c59]Réda Nouacer
, Mahmoud Hussein
, Paul Detterer
, Eugenio Villar
, Fernando Herrera
, Carlo Tieri
, Emmanuel Grolleau
:
Towards a European Network of Enabling Technologies for Drones. DroneSE/RAPIDO@HiPEAC 2023: 1-11 - 2021
- [j25]Mahmoud Hussein, Réda Nouacer, Federico Corradi
, Yassine Ouhammou, Eugenio Villar, Carlo Tieri, Rodrigo Castiñeira:
Key technologies for safe and autonomous drones. Microprocess. Microsystems 87: 104348 (2021) - [c58]Javier Merino, Raul Gomez
, Hector Posadas, Eugenio Villar:
Multilevel host-compiled simulation framework for ROS-based UAV services using ArduCopter. DCIS 2021: 1-6 - [c57]Javier Merino, Raul Gomez
, Hector Posadas, Eugenio Villar:
Modeling and Performance Estimation of Robotic Systems using ROS: Application to drone-based Services. FDL 2021: 1-8 - 2020
- [j24]Eugenio Villar, Javier Merino, Hector Posadas, Rafik Henia, Laurent Rioux:
Mega-modeling of complex, distributed, heterogeneous CPS systems. Microprocess. Microsystems 78: 103244 (2020) - [c56]Héctor Posadas, Javier Merino
, Eugenio Villar:
Data flow analysis from UML/MARTE models based on binary traces. DCIS 2020: 1-6 - [c55]Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Hector Posadas, Javier Merino
, Eugenio Villar:
Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow. DSD 2020: 117-125 - [c54]Mahmoud Hussein
, Réda Nouacer, Yassine Ouhammou, Eugenio Villar, Federico Corradi
, Carlo Tieri, Rodrigo Castiñeira:
Key Enabling Technologies for Drones. DSD 2020: 489-496
2010 – 2019
- 2019
- [c53]Héctor Posadas, Eugenio Villar, Manuel Sanchez-Renedo:
Accelerating Host-Compiled Simulation by Modifying IR Code: Industrial application in the spatial domain. DCIS 2019: 1-6 - 2017
- [j23]Kim Grüttner, Ralph Görgen, Sören Schreiner, Fernando Herrera, Pablo Peñil
, Julio L. Medina, Eugenio Villar, Gianluca Palermo
, William Fornaciari
, Carlo Brandolese, Davide Gadioli, Emanuele Vitali, Davide Zoni
, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander
, Kathrin Rosvall, Nima Khalilzad, Davide Quaglia
:
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties. Microprocess. Microsystems 51: 39-55 (2017) - [j22]Houcine Hassan, Laurence T. Yang, Jason Xue, Eugenio Villar:
Special issue on: "Heterogeneous architectures for Cyber-physical systems (HACPS)". Microprocess. Microsystems 52: 333-334 (2017) - [c52]Hector Posadas, Luis Diaz, Eugenio Villar:
Static Write Buffer Cache Modeling to Increase Host-Compiled Simulation Accuracy. DSD 2017: 47-53 - [p5]Fernando Herrera, Julio L. Medina, Eugenio Villar:
Modeling Hardware/Software Embedded Systems with UML/MARTE: A Single-Source Design Approach. Handbook of Hardware/Software Codesign 2017: 141-185 - 2016
- [j21]Hector Posadas
, Eugenio Villar
:
Using Professional Resources for Teaching Embedded SW Development. Rev. Iberoam. de Tecnol. del Aprendiz. 11(4): 248-255 (2016) - [c51]Ralph Görgen, Kim Grüttner, Fernando Herrera, Pablo Peñil
, Julio L. Medina, Eugenio Villar
, Gianluca Palermo
, William Fornaciari
, Carlo Brandolese, Davide Gadioli, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander
, Kathrin Rosvall, Davide Quaglia
:
CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties. DSD 2016: 286-293 - 2015
- [j20]Héctor Posadas, Pablo Peñil
, Alejandro Nicolás, Eugenio Villar
:
Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics. J. Syst. Archit. 61(8): 341-360 (2015) - [j19]Jiafu Wan
, Chin-Feng Lai
, Shiwen Mao, Eugenio Villar
, Subhas Mukhopadhyay
:
Innovative circuit and system design methodologies for green cyber-physical systems. Microprocess. Microsystems 39(8): 1231-1233 (2015) - [c50]Fernando Herrera, Pablo Peñil
, Eugenio Villar:
Enhancing analysability and time predictability in UML/MARTE component-based application models. FDL 2015: 122-129 - [c49]Fernando Herrera, Pablo Peñil
, Eugenio Villar:
A model-based, single-source approach to design-space exploration and synthesis of mixed-criticality systems. SCOPES 2015: 88-91 - 2014
- [j18]Fernando Herrera, Hector Posadas, Pablo Peñil
, Eugenio Villar
, Francisco Ferrero, Raúl Valencia, Gianluca Palermo
:
The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems. J. Syst. Archit. 60(1): 55-78 (2014) - [j17]Héctor Posadas, Alejandro Nicolás, Pablo Peñil
, Eugenio Villar
, Florian Broekaert, Michel Bourdellès, Albert Cohen, Mihai T. Lazarescu
, Luciano Lavagno, Andrei Sergeevich Terechko, Miguel Glassee, Manuel Prieto:
Improving the design flow for parallel and heterogeneous architectures running real-time applications: The PHARAON FP7 project. Microprocess. Microsystems 38(8): 960-975 (2014) - [j16]Héctor Posadas, Pablo Peñil
, Alejandro Nicolás, Eugenio Villar:
Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation. Microelectron. J. 45(10): 1281-1291 (2014) - [c48]Alejandro Nicolás, Pablo Peñil
, Héctor Posadas, Eugenio Villar
:
Automatic Synthesis over Multiple APIs from Uml/Marte Models for Easy Platform Mapping and Reuse. DSD 2014: 443-450 - [c47]Emad Samuel Malki Ebeid
, Franco Fummi, Davide Quaglia
, Hector Posadas, Eugenio Villar:
A framework for design space exploration and performance analysis of networked embedded systems. RAPIDO 2014: 2:1-2:8 - 2013
- [j15]Kim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar
, Carlo Brandolese, William Fornaciari
, Gianluca Palermo
, Chantal Ykman-Couvreur, Davide Quaglia
, Francisco Ferrero, Raúl Valencia:
The COMPLEX reference framework for HW/SW co-design and power management supporting platform-based design-space exploration. Microprocess. Microsystems 37(8-C): 966-980 (2013) - [c46]Rodrigo Fernández, Hector Posadas, Eugenio Villar
:
Early Performance Evaluation of Multi-OS Embedded Platforms Using Native Simulation. DSD 2013: 64-67 - [c45]Hector Posadas, Eugenio Villar
, Florian Broekaert, Michel Bourdellès, Albert Cohen, Antoniu Pop, Nhat Minh Lê, Adrien Guatto, Mihai T. Lazarescu
, Luciano Lavagno, Andrei Sergeevich Terechko, Miguel Glassee, Daniel Calvo, Eduardo de las Heras:
EU FP7-288307 Pharaon Project: Parallel and Heterogeneous Architecture for Real-Time Applications. DSD 2013: 371-378 - 2012
- [j14]Fernando Herrera, Íñigo Ugarte, Eugenio Villar
:
Towards automated implementation of adaptive systems from abstract SystemC specifications - From SystemC adaptive processes to embedded software and to synthesizable hardware descriptions. Des. Autom. Embed. Syst. 16(3): 129-160 (2012) - [c44]Fernando Herrera, Hector Posadas, Pablo Peñil
, Eugenio Villar, Francisco Ferrero, Raúl Valencia:
A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models. CODES+ISSS 2012: 529-538 - [c43]Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia:
The COMPLEX Eclipse framework for UML/MARTE specification and design space exploration of embedded systems. DASIP 2012: 1-2 - [c42]Julio Gómez López, Eugenio Villar, Gabriel Molero, Alejandro Cama-Pinto
:
Evaluation of High Performance Clusters in Private Cloud Computing Environments. DCAI 2012: 305-312 - [c41]Kim Grüttner, Philipp A. Hartmann
, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari
, Gianluca Palermo
, Chantal Ykman-Couvreur, Davide Quaglia
, Francisco Ferrero, Raúl Valencia:
COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXploration. DSD 2012: 349-358 - [c40]Fernando Herrera, Hector Posadas, Eugenio Villar, Daniel Calvo:
Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSE. DSD 2012: 692-699 - [c39]Fernando Herrera, Pablo Peñil
, Hector Posadas, Eugenio Villar
:
Model-Driven Methodology for the Development of Multi-level Executable Environments. FDL (Selected Papers) 2012: 145-164 - [c38]Fernando Herrera, Pablo Peñil, Hector Posadas, Eugenio Villar:
A model-driven methodology for the development of SystemC executable environments. FDL 2012: 177-184 - [c37]Pablo Peñil
, Héctor Posadas, Alejandro Nicolás, Eugenio Villar:
Automatic synthesis from UML/MARTE models using channel semantics. ACES-MB@MoDELS 2012: 49-54 - 2011
- [j13]Hector Posadas, Eugenio Villar, Dominique Ragot, Marcos Martínez:
Early, time-approximate modeling of multi-OS. linux platforms in a systemC co-simulation environment. Comput. Syst. Sci. Eng. 26(6) (2011) - [j12]Daniel Calvo, Pablo González, Luis Diaz, Hector Posadas, Pablo Sánchez, Eugenio Villar, Andrea Acquaviva, Enrico Macii:
A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design. J. Low Power Electron. 7(1): 2-16 (2011) - [c36]Hector Posadas, Luis Diaz, Eugenio Villar:
Fast data-cache modeling for native co-simulation. ASP-DAC 2011: 425-430 - [c35]Fernando Herrera, Eugenio Villar:
A framework for the generation from UML/MARTE models of IPXACT HW platform descriptions for multi-level performance estimation. FDL 2011: 1-8 - [c34]Fernando Herrera, Eugenio Villar, Philipp A. Hartmann:
Systemc refinement of abstract adaptive processes for implementation into Dynamically Reconfigurable Hardware. FDL 2011: 1-8 - [p4]Cristina Silvano, William Fornaciari
, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka
, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Fan Dongrui, Hao Zhang:
The MULTICUBE Design Flow. Multi-objective Design Space Exploration of Multiprocessor SoC Architectures 2011: 3-17 - [p3]Hector Posadas, Sara Real, Eugenio Villar:
M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration. Multi-objective Design Space Exploration of Multiprocessor SoC Architectures 2011: 19-50 - [p2]Marcos Martínez, David Ferruz, Hector Posadas, Eugenio Villar:
High-level modeling and exploration of a powerline communication network based on System-on-Chip. Multi-objective Design Space Exploration of Multiprocessor SoC Architectures 2011: 145-170 - [e1]Cristina Silvano, William Fornaciari
, Eugenio Villar:
Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, The MULTICUBE Approach. Springer 2011, ISBN 978-1-4419-8836-2 [contents] - 2010
- [j11]Pablo Peñil
, Julio L. Medina, Hector Posadas, Eugenio Villar:
Generating heterogeneous executable specifications in SystemC from UML/MARTE models. Innov. Syst. Softw. Eng. 6(1-2): 65-71 (2010) - [c33]Hector Posadas, Eugenio Villar:
Modeling Separate Memory Spaces in Native Co-simulation with SystemC for Design Space Exploration. ARCS Workshops 2010: 313-318 - [c32]Eugenio Villar, Fernando Herrera, Víctor Fernández:
Formal Support for Untimed SystemC Specifications: Application to High-level Synthesis. FDL 2010: 74-79 - [c31]Pablo Peñil, Fernando Herrera, Eugenio Villar:
Formal Foundations for MARTE-SystemC Interoperability. FDL 2010: 197-202 - [c30]Juan Castillo, Hector Posadas, Eugenio Villar, Marcos Martínez:
Fast instruction cache modeling for approximate timed HW/SW co-simulation. ACM Great Lakes Symposium on VLSI 2010: 191-196 - [c29]Pablo Peñil, Hector Posadas, Eugenio Villar:
Formal Modeling for UML/MARTE Concurrency Resources. ICECCS 2010: 343-348 - [c28]Roberto Varona-Gomez, Eugenio Villar:
AADS+: AADL Simulation Including the Behavioral Annex. ICECCS 2010: 379-384 - [c27]Hector Posadas, Eugenio Villar, Dominique Ragot, Marcos Martínez:
Early Modeling of Linux-Based RTOS Platforms in a SystemC Time-Approximate Co-simulation Environment. ISORC 2010: 238-244 - [c26]Cristina Silvano
, William Fornaciari
, Gianluca Palermo
, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka
, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Dongrui Fan, Hao Zhang, Shibin Tang:
MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures. ISVLSI (Selected papers) 2010: 47-63 - [c25]Wolfgang Müller, Da He, Fabian Mischkalla, Arthur Wegele, Adrian Larkham, Paul Whiston, Pablo Peñil
, Eugenio Villar, Nikolaos Mitas, Dimitrios Kritharidis, Florent Azcarate, Manuel Carballeda:
The SATURN Approach to SysML-Based HW/SW Codesign. ISVLSI (Selected papers) 2010: 151-164 - [c24]Cristina Silvano
, William Fornaciari
, Gianluca Palermo
, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka
, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Dongrui Fan, Hao Zhang, Shibin Tang:
MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures. ISVLSI 2010: 488-493 - [c23]Wolfgang Müller, Da He, Fabian Mischkalla, Arthur Wegele, Paul Whiston, Pablo Peñil
, Eugenio Villar, Nikolaos Mitas, Dimitrios Kritharidis, Florent Azcarate, Manuel Carballeda:
The SATURN Approach to SysML-Based HW/SW Codesign. ISVLSI 2010: 506-511 - [c22]Sara Real, Hector Posadas, Eugenio Villar:
L2 Cache Modeling based on address modification for Native Co-Simulation in SystemC. SIES 2010: 225-228
2000 – 2009
- 2009
- [c21]Fernando Herrera, Eugenio Villar:
Local application of simulation directed for Exhaustive Coverage of Schedulings of SystemC specifications. FDL 2009: 1-6 - [c20]Roberto Varona-Gomez, Eugenio Villar:
AADL Simulation and Performance Analysis in SystemC. ICECCS 2009: 323-328 - [c19]Hector Posadas, Eugenio Villar:
Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulation. IESS 2009: 12-23 - 2008
- [j10]Markus Damm, Jan Haase
, Christoph Grimm
, Fernando Herrera, Eugenio Villar:
Bridging MoCs in SystemC Specifications of Heterogeneous Systems. EURASIP J. Embed. Syst. 2008 (2008) - [j9]Christoph Grimm
, Axel Jantsch
, Sandeep Kumar Shukla
, Eugenio Villar:
C-Based Design of Heterogeneous Embedded Systems. EURASIP J. Embed. Syst. 2008 (2008) - [c18]Eugenio Villar, Axel Jantsch, Christoph Grimm, Tim Kogel:
Heterogeneous System-level Specification Using SystemC. DATE 2008 - [c17]Fernando Herrera, Eugenio Villar, Philipp A. Hartmann:
Specification of Adaptive HW/SW Systems in SystemC. FDL 2008: 61-65 - 2007
- [j8]Fernando Herrera, Eugenio Villar
:
A framework for heterogeneous specification and design of electronic embedded systems in SystemC. ACM Trans. Design Autom. Electr. Syst. 12(3): 22:1-22:31 (2007) - [c16]Fernando Herrera, Eugenio Villar, Christoph Grimm, Markus Damm, Jan Haase:
A general approach to the interoperability of HetSC and SystemC-AMS. FDL 2007: 32-37 - [c15]Hector Posadas, David Quijano, Eugenio Villar, Marcos Martínez:
Protocol Bus Modeling using inheritance with TLM2.0. FDL 2007: 80-85 - [c14]Andreas Herrholz, Frank Oppenheimer, Philipp A. Hartmann, Andreas Schallenberg, Wolfgang Nebel, Christoph Grimm
, Markus Damm, Jan Haase
, Florian Brame, Fernando Herrera, Eugenio Villar
, Ingo Sander
, Axel Jantsch, Anne-Marie Fouilliart, Marcos Martínez:
The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. FPL 2007: 396-401 - [c13]Eduardo de las Heras, Eugenio Villar:
Specification for SystemC-AADL interoperability. WISES 2007: 76-86 - 2006
- [c12]Hector Posadas, Jesús Ádamez, Pablo Sánchez, Eugenio Villar
, Francisco Blasco:
POSIX modeling in SystemC. ASP-DAC 2006: 485-490 - [c11]Fernando Herrera, Eugenio Villar:
A framework for embedded system specification under different models of computation in SystemC. DAC 2006: 911-914 - [c10]Fernando Herrera, Eugenio Villar:
Extension of the SystemC Kernel for Simulation Coverage. FDL 2006: 161-168 - 2005
- [j7]Hector Posadas, Jesús Ádamez, Eugenio Villar
, Francisco Blasco, F. Escuder:
RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model. Des. Autom. Embed. Syst. 10(4): 209-227 (2005) - [c9]Fernando Herrera, Eugenio Villar:
Mixing Synchronous Reactive and Untimed Models of Computation. FDL 2005: 315-329 - 2004
- [j6]Hector Posadas, Fernando Herrera, Víctor Fernández
, Pablo Sánchez, Eugenio Villar
, Francisco Blasco:
Single Source Design Environment for Embedded Systems Based on SystemC. Des. Autom. Embed. Syst. 9(4): 293-312 (2004) - [c8]Hector Posadas, Fernando Herrera, Pablo Sánchez, Eugenio Villar, Francisco Blasco:
System-Level Performance Analysis in SystemC. DATE 2004: 378-383 - [c7]Fernando Herrera, Pablo Sánchez, Eugenio Villar:
Heterogeneous System-Level Specification in SystemC. FDL 2004: 404-416 - 2003
- [c6]Fernando Herrera, Hector Posadas, Pablo Sánchez, Eugenio Villar:
Systemic Embedded Software Generation from SystemC. DATE 2003: 10142-10149 - [c5]Fernando Herrera, Pablo Sánchez, Eugenio Villar
:
Modeling of CSP, KPN and SR Systems with SystemC. FDL 2003: 572-583 - [p1]Fernando Herrera, Héctor Posadas, Pablo Sánchez, Eugenio Villar:
Systematic Embedded Software Generation from Systemc. Embedded Software for SoC 2003: 83-93 - 2001
- [c4]Daniel Gajski, Eugenio Villar, Wolfgang Rosenstiel, Vassilios Gerousis, D. Barton, Jonas Plantin, S. E. Ericsson, Patrizia Cavalloro, Gjalt G. de Jong:
C/C++: progress or deadlock in system-level specification. DATE 2001: 136-137 - 2000
- [j5]Giulio Gorla, Eduard Moser, Wolfgang Nebel, Eugenio Villar
:
System Specification Experiments on a Common Benchmark. IEEE Des. Test Comput. 17(3): 22-32 (2000)
1990 – 1999
- 1999
- [c3]Adrian López, Maite Veiga, Eugenio Villar:
Hardware/Software Embedded System Specifiaction and Design Using Ada and VHDL. Ada-Europe 1999: 356-370 - 1998
- [j4]Pedro Tabuenca, Pablo Sánchez, Eugenio Villar
:
An algorithm for clock cycle selection in behavioral synthesis. J. Syst. Archit. 44(9-10): 773-786 (1998) - 1996
- [j3]Masaharu Imai, Eugenio Villar:
ASPDAC 1995: HDL synthesizability and interoperability. IEEE Des. Test Comput. 13(1): 3-4 (1996) - [j2]Manfred Selz, Wolfgang Ecker, Eugenio Villar
:
VHDL synthesis description portability: The need for Level synthesis subsets. J. Syst. Archit. 42(2): 105-116 (1996) - 1995
- [c2]Masaharu Imai, Eugenio Villar:
Future direction of synthesizability and interoperability of HDL's: part 1. ASP-DAC 1995 - [c1]Eugenio Villar, Masaharu Imai:
Future direction of synthesizabilty and interoperability of HDL's: part 2. ASP-DAC 1995 - 1992
- [j1]E. Randon, P. Sanchez, Eugenio Villar
:
ESP, a structure synthesis program. Microprocess. Microprogramming 34(1-5): 143-145 (1992)
Coauthor Index
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