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ORCIDSanjiv Narayan
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2010 – 2019
- 2014
[c18]Faisal Alam, Preeti Ranjan Panda, Nikhil Tripathi, Namita Sharma, Sanjiv Narayan:
Energy optimization in Android applications through wakelock placement. DATE 2014: 1-4
2000 – 2009
- 2003
- [c17]G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja:
Graph Transformations for Improved Tree Height Reduction. VLSI Design 2003: 474-479
1990 – 1999
- 1998
- [j5]Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong:
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. IEEE Trans. Very Large Scale Integr. Syst. 6(1): 84-100 (1998) - [c16]Daniel Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong:
System-level exploration with SpecSyn. DAC 1998: 812-817 - 1996
- [j4]En-Shou Chang, Daniel Gajski, Sanjiv Narayan:
An optimal clock period selection method based on slack minimization criteria. ACM Trans. Design Autom. Electr. Syst. 1(3): 352-370 (1996) - [j3]Daniel D. Gajski, Sanjiv Narayan, Loganath Ramachandran, Frank Vahid, Peter Fung:
System design methodologies: aiming at the 100 h design cycle. IEEE Trans. Very Large Scale Integr. Syst. 4(1): 70-82 (1996) - [c15]Sanjiv Narayan, Daniel D. Gajski:
Rapid performance estimation for system design. EURO-DAC 1996: 206-211 - 1995
- [j2]Frank Vahid, Sanjiv Narayan, Daniel D. Gajski:
SpecCharts: a VHDL front-end for embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 694-706 (1995) - [c14]Sanjiv Narayan, Daniel Gajski:
Interfacing Incompatible Protocols Using Interface Process Generation. DAC 1995: 468-473 - [c13]Jie Gong, Daniel D. Gajski, Sanjiv Narayan:
Software estimation using a generic-processor model. ED&TC 1995: 498-502 - 1994
- [c12]Sanjiv Narayan, Daniel Gajski:
Protocol Generation for Communication Channels. DAC 1994: 547-551 - [c11]Loganath Ramachandran, Daniel D. Gajski, Sanjiv Narayan, Frank Vahid, Peter Fung:
100-hour design cycle: a test case. EURO-DAC 1994: 144-149 - [c10]Sanjiv Narayan, Daniel Gajski:
Synthesis of System-Level Bus Interfaces. EDAC-ETC-EUROASIC 1994: 395-399 - [c9]Daniel Gajski, Frank Vahid, Sanjiv Narayan:
A System-Design Methodology: Executable-Specification Refinement. EDAC-ETC-EUROASIC 1994: 458-463 - [c8]Frank Vahid, Daniel D. Gajski, Sanjiv Narayan:
A transformation for integrating VHDL behavioral specification with synthesis and software generation. EURO-DAC 1994: 552-557 - 1993
- [c7]Sanjiv Narayan, Daniel D. Gajski:
Features supporting system-level specification in HDLs. EURO-DAC 1993: 540-545 - [c6]Loganath Ramachandran, Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
Synthesis of functions and procedures in behavioral VHDL. EURO-DAC 1993: 560-565 - 1992
- [j1]Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
System Specification with the SpecCharts Language. IEEE Des. Test Comput. 9(4): 6-13 (1992) - [c5]Sanjiv Narayan, Daniel D. Gajski:
System clock estimation based on clock slack minimization. EURO-DAC 1992: 66-71 - [c4]Loganath Ramachandran, Frank Vahid, Sanjiv Narayan, Daniel D. Gajski:
Semantics and synthesis of signals in behavioral VHDL. EURO-DAC 1992: 616-621 - [c3]Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
System Level Specification and Synthesis. VLSI Design 1992: 103-108 - 1991
- [c2]Sanjiv Narayan, Frank Vahid, Daniel D. Gajski:
Translating system specifications to VHDL. EURO-DAC 1991: 390-394 - [c1]Sanjiv Narayan, Frank Vahid, Daniel Gajski:
System Specification and Synthesis with the SpecCharts Language. ICCAD 1991: 266-269
Coauthor Index
aka: Daniel D. Gajski
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