Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. - Chang, Kyungwook; Sinha, Saurabh; Cline, Brian; Yeric, Greg; Lim, Sung Kyu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Extreme Temperature (> 200 °C), Radiation Hard (> 1 Mrad), Dense (sub-50 nm CD), Fast (2 ns write pulses), Non-Volatile Memory Technology. - Suryavanshi, Saurabh V.; Yeric, Greg; Irby, Max; Huang, X. M. Henry; Rosendale, Glen; Shifren, Lucian (2022)

Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor. - Lee, Chi-Shuen; Cline, Brian; Sinha, Saurabh; Yeric, Greg; Wong, H.-S. Philip (CoRR, 2021)

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling. - Sinha, Saurabh; Xu, Xiaoqing; Bhargava, Mudit; Das, Shidhartha; Cline, Brian; Yeric, Greg (CoRR, 2020)

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. - Chang, Kyungwook; Das, Shidhartha; Sinha, Saurabh; Cline, Brian; Yeric, Greg; Lim, Sung Kyu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

IC Design After Moore's Law. - Yeric, Greg (2019)

Standard Cell Library Design and Optimization Methodology for ASAP7 PDK. - Xu, Xiaoqing; Shah, Nishi; Evans, Andrew; Sinha, Saurabh; Cline, Brian; Yeric, Greg (CoRR, 2018)

Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node. - Chang, Kyungwook; Acharya, Kartik; Sinha, Saurabh; Cline, Brian; Yeric, Greg; Lim, Sung Kyu (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). - Xu, Xiaoqing; Shah, Nishi; Evans, Andrew; Sinha, Saurabh; Cline, Brian; Yeric, Greg (2017)

DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node. - Ou, Jiaojiao; Xu, Xiaoqing; Cline, Brian; Yeric, Greg; Pan, David Z. (2017)

Frequency and time domain analysis of power delivery network for monolithic 3D ICs. - Chang, Kyungwook; Das, Shidhartha; Sinha, Saurabh; Cline, Brian; Yeric, Greg; Lim, Sung Kyu (2017)

Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches. - Aitken, Robert C.; Chandra, Vikas; Cline, Brian; Das, Shidhartha; Pietromonaco, David; Shifren, Lucian; Sinha, Saurabh; Yeric, Greg (IET Comput. Digit. Tech., 2016)

ASAP7: A 7-nm finFET predictive process design kit. - Clark, Lawrence T.; Vashishtha, Vinay; Shifren, Lucian; Gujja, Aditya; Sinha, Saurabh; Cline, Brian; Ramamurthy, Chandarasekaran; Yeric, Greg (Microelectron. J., 2016)

Match-making for monolithic 3D IC: finding the right technology node. - Chang, Kyungwook; Sinha, Saurabh; Cline, Brian; Yeric, Greg; Lim, Sung Kyu (2016)

At the core of system scaling. - Yeric, Greg (2016)

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. - Chang, Kyungwook; Sinha, Saurabh; Cline, Brian; Southerland, Raney; Doherty, Michael; Yeric, Greg; Lim, Sung Kyu (2016)

Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. - Kim, Kwang Min; Sinha, Saurabh; Cline, Brian; Yeric, Greg; Lim, Sung Kyu (2016)

Monolithic 3D IC design: Power, performance, and area impact at 7nm. - Acharya, Kartik; Chang, Kyungwook; Ku, Bon Woong; Panth, Shreepad; Sinha, Saurabh; Cline, Brian; Yeric, Greg; Lim, Sung Kyu (2016)

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization. - Xu, Xiaoqing; Cline, Brian; Yeric, Greg; Yu, Bei; Pan, David Z. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Power benefit study of monolithic 3D IC at the 7nm technology node. - Chang, Kyungwook; Acharya, Kartik; Sinha, Saurabh; Cline, Brian; Yeric, Greg; Lim, Sung Kyu (2015)

Circuit design perspectives for Ge FinFET at 10nm and beyond. - Sinha, Saurabh; Shifren, Lucian; Chandra, Vikas; Cline, Brian; Yeric, Greg; Aitken, Robert C.; Cheng, Bingjie; Brown, Andrew R.; Riddet, Craig; Alexandar, C.; Millar, Campbell; Asenov, Asen (2015)

Physical design and FinFETs. - Aitken, Robert C.; Yeric, Greg; Cline, Brian; Sinha, Saurabh; Shifren, Lucian; Iqbal, Imran; Chandra, Vikas (2014)

Self-aligned double patterning aware pin access and standard cell layout co-optimization. - Xu, Xiaoqing; Cline, Brian; Yeric, Greg; Yu, Bei; Pan, David Z. (2014)

Design, technology and yield in the post-moore era. - Yeric, Greg (2014)

The past present and future of design-technology co-optimization. - Yeric, Greg; Cline, Brian; Sinha, Saurabh; Pietromonaco, David; Chandra, Vikas; Aitken, Rob (2013)

Exploring sub-20nm FinFET design with predictive technology models. - Sinha, Saurabh; Yeric, Greg; Chandra, Vikas; Cline, Brian; Cao, Yu (2012)

Design benchmarking to 7nm with FinFET predictive technology models. - Sinha, Saurabh; Cline, Brian; Yeric, Greg; Chandra, Vikas; Cao, Yu (2012)

Correlating models and silicon for improved parametric yield. - Aitken, Rob; Yeric, Greg; Flynn, David (2011)

Making Manufacturing Work For You. - Venkataraman, Srikanth; Puri, Ruchir; Griffith, Steve; Oberai, Ankush; Madge, Robert; Yeric, Greg; Ng, Walter; Zorian, Yervant (2007)

Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below. - Yeric, Greg; Cohen, Ethan; Garcia, John; Davis, Kurt; Salem, Esam; Green, Gary (IEEE Des. Test Comput., 2005)

Universal MOSFET hole mobility degradation models for circuit simulation. - Agostinelli, Victor Martin, Jr.; Yeric, Gregory Munson; Tasch, A. F., Jr. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Improved universal MOSFET electron mobility degradation models for circuit simulation. - Yue, C. Patrick; Agostinelli, Victor Martin, Jr.; Yeric, Gregory Munson; Tasch, A. F., Jr. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

A universal MOSFET mobility degradation model for circuit simulation. - Yeric, Gregory Munson; Tasch, A. F., Jr.; Banerjee, Sanjay K. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)