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ORCIDBibTeX records: Greg Yeric
@article{DBLP:journals/tcad/ChangSCYL22,
author = {Kyungwook Chang and
Saurabh Sinha and
Brian Cline and
Greg Yeric and
Sung Kyu Lim},
title = {Design-Aware Partitioning-Based 3-D {IC} Design Flow With 2-D Commercial
Tools},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {3},
pages = {410--423},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3065005},
doi = {10.1109/TCAD.2021.3065005},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangSCYL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/imw2/SuryavanshiYIHR22,
author = {Saurabh V. Suryavanshi and
Greg Yeric and
Max Irby and
X. M. Henry Huang and
Glen Rosendale and
Lucian Shifren},
title = {Extreme Temperature ({\textgreater} 200 {\textdegree}C), Radiation
Hard ({\textgreater} 1 Mrad), Dense (sub-50 nm CD), Fast {(2} ns write
pulses), Non-Volatile Memory Technology},
booktitle = {{IEEE} International Memory Workshop, {IMW} 2022, Dresden, Germany,
May 15-18, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/IMW52921.2022.9779251},
doi = {10.1109/IMW52921.2022.9779251},
timestamp = {Fri, 16 Jun 2023 10:03:33 +0200},
biburl = {https://dblp.org/rec/conf/imw2/SuryavanshiYIHR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2109-07915,
author = {Chi{-}Shuen Lee and
Brian Cline and
Saurabh Sinha and
Greg Yeric and
H.{-}S. Philip Wong},
title = {Device-to-System Performance Evaluation: from Transistor/Interconnect
Modeling to {VLSI} Physical Design and Neural-Network Predictor},
journal = {CoRR},
volume = {abs/2109.07915},
year = {2021},
url = {https://arxiv.org/abs/2109.07915},
eprinttype = {arXiv},
eprint = {2109.07915},
timestamp = {Wed, 22 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2109-07915.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2005-10866,
author = {Saurabh Sinha and
Xiaoqing Xu and
Mudit Bhargava and
Shidhartha Das and
Brian Cline and
Greg Yeric},
title = {Stack up your chips: Betting on 3D integration to augment Moore's
Law scaling},
journal = {CoRR},
volume = {abs/2005.10866},
year = {2020},
url = {https://arxiv.org/abs/2005.10866},
eprinttype = {arXiv},
eprint = {2005.10866},
timestamp = {Thu, 28 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2005-10866.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangDSCYL19,
author = {Kyungwook Chang and
Shidhartha Das and
Saurabh Sinha and
Brian Cline and
Greg Yeric and
Sung Kyu Lim},
title = {System-Level Power Delivery Network Analysis and Optimization for
Monolithic 3-D ICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {4},
pages = {888--898},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2897589},
doi = {10.1109/TVLSI.2019.2897589},
timestamp = {Sun, 19 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangDSCYL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/Yeric19,
author = {Greg Yeric},
title = {{IC} Design After Moore's Law},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2019, Austin,
TX, USA, April 14-17, 2019},
pages = {1--150},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CICC.2019.8780343},
doi = {10.1109/CICC.2019.8780343},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/Yeric19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1807-11396,
author = {Xiaoqing Xu and
Nishi Shah and
Andrew Evans and
Saurabh Sinha and
Brian Cline and
Greg Yeric},
title = {Standard Cell Library Design and Optimization Methodology for {ASAP7}
{PDK}},
journal = {CoRR},
volume = {abs/1807.11396},
year = {2018},
url = {http://arxiv.org/abs/1807.11396},
eprinttype = {arXiv},
eprint = {1807.11396},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1807-11396.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangASCYL17,
author = {Kyungwook Chang and
Kartik Acharya and
Saurabh Sinha and
Brian Cline and
Greg Yeric and
Sung Kyu Lim},
title = {Impact and Design Guideline of Monolithic 3-D {IC} at the 7-nm Technology
Node},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {7},
pages = {2118--2129},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2686426},
doi = {10.1109/TVLSI.2017.2686426},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangASCYL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/XuSESCY17,
author = {Xiaoqing Xu and
Nishi Shah and
Andrew Evans and
Saurabh Sinha and
Brian Cline and
Greg Yeric},
editor = {Sri Parameswaran},
title = {Standard cell library design and optimization methodology for {ASAP7}
{PDK:} (Invited paper)},
booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
pages = {999--1004},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ICCAD.2017.8203890},
doi = {10.1109/ICCAD.2017.8203890},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iccad/XuSESCY17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/OuXCYP17,
author = {Jiaojiao Ou and
Xiaoqing Xu and
Brian Cline and
Greg Yeric and
David Z. Pan},
title = {{DTCO} for {DSA-MP} Hybrid Lithography with Double-BCP Materials in
Sub-7nm Node},
booktitle = {2017 {IEEE} International Conference on Computer Design, {ICCD} 2017,
Boston, MA, USA, November 5-8, 2017},
pages = {403--410},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ICCD.2017.70},
doi = {10.1109/ICCD.2017.70},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/OuXCYP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ChangDSCYL17,
author = {Kyungwook Chang and
Shidhartha Das and
Saurabh Sinha and
Brian Cline and
Greg Yeric and
Sung Kyu Lim},
title = {Frequency and time domain analysis of power delivery network for monolithic
3D ICs},
booktitle = {2017 {IEEE/ACM} International Symposium on Low Power Electronics and
Design, {ISLPED} 2017, Taipei, Taiwan, July 24-26, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISLPED.2017.8009180},
doi = {10.1109/ISLPED.2017.8009180},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/ChangDSCYL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/AitkenCCDPSSY16,
author = {Robert C. Aitken and
Vikas Chandra and
Brian Cline and
Shidhartha Das and
David Pietromonaco and
Lucian Shifren and
Saurabh Sinha and
Greg Yeric},
title = {Predicting future complementary metal-oxide-semiconductor technology
- challenges and approaches},
journal = {{IET} Comput. Digit. Tech.},
volume = {10},
number = {6},
pages = {315--322},
year = {2016},
url = {https://doi.org/10.1049/iet-cdt.2015.0210},
doi = {10.1049/IET-CDT.2015.0210},
timestamp = {Wed, 27 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/AitkenCCDPSSY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/ClarkVSGSCRY16,
author = {Lawrence T. Clark and
Vinay Vashishtha and
Lucian Shifren and
Aditya Gujja and
Saurabh Sinha and
Brian Cline and
Chandarasekaran Ramamurthy and
Greg Yeric},
title = {{ASAP7:} {A} 7-nm finFET predictive process design kit},
journal = {Microelectron. J.},
volume = {53},
pages = {105--115},
year = {2016},
url = {https://doi.org/10.1016/j.mejo.2016.04.006},
doi = {10.1016/J.MEJO.2016.04.006},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/ClarkVSGSCRY16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChangSCYL16,
author = {Kyungwook Chang and
Saurabh Sinha and
Brian Cline and
Greg Yeric and
Sung Kyu Lim},
title = {Match-making for monolithic 3D {IC:} finding the right technology
node},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {77:1--77:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2898043},
doi = {10.1145/2897937.2898043},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/ChangSCYL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/Yeric16,
author = {Greg Yeric},
title = {At the core of system scaling},
booktitle = {{ESSCIRC} Conference 2016: 42\({}^{\mbox{nd}}\) European Solid-State
Circuits Conference, Lausanne, Switzerland, September 12-15, 2016},
pages = {1--2},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ESSCIRC.2016.7598230},
doi = {10.1109/ESSCIRC.2016.7598230},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/Yeric16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChangSCSDYL16,
author = {Kyungwook Chang and
Saurabh Sinha and
Brian Cline and
Raney Southerland and
Michael Doherty and
Greg Yeric and
Sung Kyu Lim},
editor = {Frank Liu},
title = {Cascade2D: {A} design-aware partitioning approach to monolithic 3D
{IC} with 2D commercial tools},
booktitle = {Proceedings of the 35th International Conference on Computer-Aided
Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
pages = {130},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2966986.2967013},
doi = {10.1145/2966986.2967013},
timestamp = {Fri, 23 Jun 2023 22:29:48 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ChangSCSDYL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KimSCYL16,
author = {Kwang Min Kim and
Saurabh Sinha and
Brian Cline and
Greg Yeric and
Sung Kyu Lim},
title = {Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power
Benefit Study},
booktitle = {Proceedings of the 2016 International Symposium on Low Power Electronics
and Design, {ISLPED} 2016, San Francisco Airport, CA, USA, August
08 - 10, 2016},
pages = {70--75},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2934583.2934623},
doi = {10.1145/2934583.2934623},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/KimSCYL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/AcharyaCKPSCYL16,
author = {Kartik Acharya and
Kyungwook Chang and
Bon Woong Ku and
Shreepad Panth and
Saurabh Sinha and
Brian Cline and
Greg Yeric and
Sung Kyu Lim},
title = {Monolithic 3D {IC} design: Power, performance, and area impact at
7nm},
booktitle = {17th International Symposium on Quality Electronic Design, {ISQED}
2016, Santa Clara, CA, USA, March 15-16, 2016},
pages = {41--48},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISQED.2016.7479174},
doi = {10.1109/ISQED.2016.7479174},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/AcharyaCKPSCYL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuCYYP15,
author = {Xiaoqing Xu and
Brian Cline and
Greg Yeric and
Bei Yu and
David Z. Pan},
title = {Self-Aligned Double Patterning Aware Pin Access and Standard Cell
Layout Co-Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {34},
number = {5},
pages = {699--712},
year = {2015},
url = {https://doi.org/10.1109/TCAD.2015.2399439},
doi = {10.1109/TCAD.2015.2399439},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuCYYP15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ChangASCYL15,
author = {Kyungwook Chang and
Kartik Acharya and
Saurabh Sinha and
Brian Cline and
Greg Yeric and
Sung Kyu Lim},
title = {Power benefit study of monolithic 3D {IC} at the 7nm technology node},
booktitle = {{IEEE/ACM} International Symposium on Low Power Electronics and Design,
{ISLPED} 2015, Rome, Italy, July 22-24, 2015},
pages = {201--206},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISLPED.2015.7273514},
doi = {10.1109/ISLPED.2015.7273514},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/ChangASCYL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/SinhaSCCYACBRAM15,
author = {Saurabh Sinha and
Lucian Shifren and
Vikas Chandra and
Brian Cline and
Greg Yeric and
Robert C. Aitken and
Bingjie Cheng and
Andrew R. Brown and
Craig Riddet and
C. Alexandar and
Campbell Millar and
Asen Asenov},
title = {Circuit design perspectives for Ge FinFET at 10nm and beyond},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {57--60},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085398},
doi = {10.1109/ISQED.2015.7085398},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/SinhaSCCYACBRAM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/AitkenYCSSIC14,
author = {Robert C. Aitken and
Greg Yeric and
Brian Cline and
Saurabh Sinha and
Lucian Shifren and
Imran Iqbal and
Vikas Chandra},
editor = {Cliff C. N. Sze and
Azadeh Davoodi},
title = {Physical design and FinFETs},
booktitle = {International Symposium on Physical Design, ISPD'14, Petaluma, CA,
USA, March 30 - April 02, 2014},
pages = {65--68},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2560519.2565871},
doi = {10.1145/2560519.2565871},
timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
biburl = {https://dblp.org/rec/conf/ispd/AitkenYCSSIC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/XuCYYP14,
author = {Xiaoqing Xu and
Brian Cline and
Greg Yeric and
Bei Yu and
David Z. Pan},
editor = {Cliff C. N. Sze and
Azadeh Davoodi},
title = {Self-aligned double patterning aware pin access and standard cell
layout co-optimization},
booktitle = {International Symposium on Physical Design, ISPD'14, Petaluma, CA,
USA, March 30 - April 02, 2014},
pages = {101--108},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2560519.2560530},
doi = {10.1145/2560519.2560530},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/XuCYYP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Yeric14,
author = {Greg Yeric},
title = {Design, technology and yield in the post-moore era},
booktitle = {2014 International Test Conference, {ITC} 2014, Seattle, WA, USA,
October 20-23, 2014},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/TEST.2014.7035310},
doi = {10.1109/TEST.2014.7035310},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/Yeric14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/YericCSPCA13,
author = {Greg Yeric and
Brian Cline and
Saurabh Sinha and
David Pietromonaco and
Vikas Chandra and
Rob Aitken},
title = {The past present and future of design-technology co-optimization},
booktitle = {Proceedings of the {IEEE} 2013 Custom Integrated Circuits Conference,
{CICC} 2013, San Jose, CA, USA, September 22-25, 2013},
pages = {1--8},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/CICC.2013.6658476},
doi = {10.1109/CICC.2013.6658476},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/YericCSPCA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SinhaYCCC12,
author = {Saurabh Sinha and
Greg Yeric and
Vikas Chandra and
Brian Cline and
Yu Cao},
editor = {Patrick Groeneveld and
Donatella Sciuto and
Soha Hassoun},
title = {Exploring sub-20nm FinFET design with predictive technology models},
booktitle = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
Francisco, CA, USA, June 3-7, 2012},
pages = {283--288},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2228360.2228414},
doi = {10.1145/2228360.2228414},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/SinhaYCCC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/SinhaCYCC12,
author = {Saurabh Sinha and
Brian Cline and
Greg Yeric and
Vikas Chandra and
Yu Cao},
editor = {Naresh R. Shanbhag and
Massimo Poncino and
Pai H. Chou and
Ajith Amerasekera},
title = {Design benchmarking to 7nm with FinFET predictive technology models},
booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'12,
Redondo Beach, CA, {USA} - July 30 - August 01, 2012},
pages = {15--20},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2333660.2333666},
doi = {10.1145/2333660.2333666},
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@inproceedings{DBLP:conf/date/AitkenYF11,
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timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/AitkenYF11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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Steve Griffith and
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title = {Making Manufacturing Work For You},
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publisher = {{IEEE}},
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timestamp = {Tue, 29 Jul 2014 01:00:00 +0200},
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bibsource = {dblp computer science bibliography, https://dblp.org}
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@article{DBLP:journals/tcad/AgostinelliYT93,
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bibsource = {dblp computer science bibliography, https://dblp.org}
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biburl = {https://dblp.org/rec/journals/tcad/YueAYT93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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bibsource = {dblp computer science bibliography, https://dblp.org}
}
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