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ORCIDBehjat Forouzandeh
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- affiliation: University of Tehran, Iran
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2020 – today
- 2024
[j22]Abdolvahab Khalili Sadaghiani, Behjat Forouzandeh:
High-performance power spectral/bispectral estimator for biomedical signal processing applications using novel memory-based FFT processor. Integr. 99: 102241 (2024)- 2023
- [j21]Abdolvahab Khalili Sadaghiani, Samad Sheikhaei, Behjat Forouzandeh:
Image Interpolation Based on 2D-DWT with Novel Regularity-Preserving Algorithm Using RLS Adaptive Filters. Int. J. Image Graph. 23(5): 2350039:1-2350039:20 (2023) - [j20]Abdolvahab Khalili Sadaghiani, Behjat Forouzandeh:
Novel low-power pipelined DCT processor for real-time IoT applications. J. Real Time Image Process. 20(3): 49 (2023) - 2022
- [j19]Abdolvahab Khalili Sadaghiani, Samad Sheikhaei
, Behjat Forouzandeh:
Low Complexity Multiplierless Welch Estimator Based on Memory-Based FFT. J. Circuits Syst. Comput. 31(15): 2220003:1-2220003:15 (2022) - [j18]Abdolvahab Khalili Sadaghiani, Behjat Forouzandeh:
Low-power hardware-efficient memory-based DCT processor. J. Real Time Image Process. 19(6): 1105-1121 (2022) - [j17]Abdolvahab Khalili Sadaghiani, Behjat Forouzandeh:
Image interpolation based on 2D-DWT and HDP-HMM. Pattern Anal. Appl. 25(2): 361-377 (2022) - 2020
- [j16]Parham Taghinia Jelodari, Mojtaba Parsa Kordasiabi, Samad Sheikhaei, Behjat Forouzandeh:
An O(1) time complexity sorting network for small number of inputs with hardware implementation. Microprocess. Microsystems 77: 103203 (2020)
2010 – 2019
- 2019
- [j15]Parham Taghinia Jelodari, Mojtaba Parsa Kordasiabi, Samad Sheikhaei, Behjat Forouzandeh:
FPGA implementation of an adaptive window size image impulse noise suppression system. J. Real Time Image Process. 16(6): 2015-2026 (2019) - 2017
- [j14]Mahdieh Grailoo, Bijan Alizadeh, Behjat Forouzandeh:
Improved Range Analysis in Fixed-Point Polynomial Data-Path. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(11): 1925-1929 (2017) - [j13]Mehrnaz Ahmadi, Bijan Alizadeh, Behjat Forouzandeh:
A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(1): 100-110 (2017) - 2016
- [j12]Mahdieh Grailoo, Bijan Alizadeh, Behjat Forouzandeh:
UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications. IEEE Trans. Circuits Syst. II Express Briefs 63-II(10): 994-998 (2016) - [c12]Hossein Aghababa, Mohammadreza Kolahdouz, Behjat Forouzandeh:
Analysis of stress effects on timing of nano-scaled CMOS digital integrated circuits. PATMOS 2016: 120-127 - 2015
- [j11]Soolmaz Abbasalizadeh, Samad Sheikhaei, Behjat Forouzandeh:
A 0.8-V supply bulk-driven operational transconductance amplifier and Gm-C filter in 0.18 µm CMOS process. Int. J. Circuit Theory Appl. 43(7): 929-943 (2015) - [c11]Mehrnaz Ahmadi, Bijan Alizadeh, Behjat Forouzandeh:
A Timing Error Mitigation Technique for High Performance Designs. ISVLSI 2015: 428-433 - 2014
- [c10]Vahid Janfaza, Bahjat Forouzandeh, Payman Behnam, Mohammadreza Najafi:
Hybrid history-based test overlapping to reduce test application time. EWDTS 2014: 1-4 - [c9]Vahid Janfaza, Paniz Foroutan, Bahjat Forouzandeh, M. H. Haghbayan:
A mathematical model for estimating acceptable ratio of test patterns. EWDTS 2014: 1-4 - [c8]Vahid Janfaza, Payman Behnam, Bahjat Forouzandeh, Bijan Alizadeh:
A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression. ISVLSI 2014: 220-225 - 2013
- [c7]Vahid Janfaza, Bahjat Forouzandeh, Payman Behnam, Mohammadreza Najafi:
Hybrid history-based test overlapping to reduce test application time. EWDTS 2013: 1-4 - 2012
- [j10]Hossein Aghababa, Behzad Ebrahimi, Mehdi Saremi, Vahid Moalemi, Behjat Forouzandeh:
G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systems. IEICE Electron. Express 9(10): 881-887 (2012) - [j9]Hossein Aghababa, Alireza Khosropour, Ali Afzali-Kusha, Behjat Forouzandeh, Massoud Pedram:
Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution. IET Circuits Devices Syst. 6(5): 273-278 (2012) - [j8]Hossein Aghababa, Behjat Forouzandeh, Ali Afzali-Kusha:
High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility. J. Zhejiang Univ. Sci. C 13(6): 460-471 (2012) - [j7]Pedram Payandehnia, Samad Sheikhaei, Aliazam Abbasfar, Behjat Forouzandeh:
A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE. Microelectron. J. 43(12): 1029-1037 (2012) - 2011
- [j6]Hossein Aghababa, Reza Asadpour, Ali Afzali-Kusha, Behjat Forouzandeh:
Finding optimum value of numerical aperture for the best aerial image quality. IEICE Electron. Express 8(11): 879-883 (2011) - [c6]Pedram Payandehnia, Behjat Forouzandeh, Aliazam Abbasfar, Samad Sheikhaei, Kambiz Nanbakhsh:
A 12.5Gb/s active-inductor based transmitter for I/O applications. ECCTD 2011: 186-189 - [c5]Alireza Khosropour, Hossein Aghababa, Behjat Forouzandeh:
Quantum Division Circuit Based on Restoring Division Algorithm. ITNG 2011: 1037-1040 - [c4]Alireza Khosropour, Hossein Aghababa, Ali Afzali-Kusha, Behjat Forouzandeh:
Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution. PATMOS 2011: 173-179 - 2010
- [j5]Farzan Jazayeri, Farshid Raissi, Behjat Forouzandeh:
Low-power and high-performance Automatic Gain Control systems based on nanoscale Field Effect Diode and SOI-MOSFET. IEICE Electron. Express 7(5): 371-376 (2010) - [j4]Farzan Jazayeri, Ahmad Sammak, Behjat Forouzandeh, Farshid Raissi:
A novel ultra low-energy sub-threshold inverter based on nanoscale Field Effect Diode. IEICE Electron. Express 7(13): 906-912 (2010) - [c3]Hossein Aghababa, Mahmoud Zangeneh, Ali Afzali-Kusha, Behjat Forouzandeh:
Statistical delay modeling of read operation of SRAMs due to channel length variation. ISCAS 2010: 2502-2505
2000 – 2009
- 2009
- [j3]Farzan Jazayeri, Behjat Forouzandeh, Farshid Raissi:
Low-power variable gain amplifier with wide UGBW based on nanoscale Field Effect Diode. IEICE Electron. Express 6(1): 51-57 (2009) - [c2]Mahmoud Zangeneh, Hossein Aghababa, Behjat Forouzandeh:
Design of a two-capacitor sample & hold circuit using a two-stage OTA with hybrid cascode compensation. ECCTD 2009: 493-498 - 2008
- [j2]Morteza Damavandpeyma, Rasoul Yousefi, Behjat Forouzandeh:
Delay testing of PD-SOI circuits. IEICE Electron. Express 5(12): 437-441 (2008) - 2007
- [j1]Mohammad Mahdi Khafaji, Mahmoud Kamarei, Behjat Forouzandeh:
Modified analytical model for subthreshold current in short channel MOSFET's. IEICE Electron. Express 4(3): 114-120 (2007) - 2006
- [c1]Fatemeh Aezinia, Behjat Forouzandeh:
A Novel Low Power NOR gate in SOI CMOS Technology. APCCAS 2006: 1403-1405
Coauthor Index
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last updated on 2024-08-07 21:32 CEST by the dblp team
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