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2010 – 2019
- 2016
[j32]Weiwu Hu, Yifu Zhang, Jie Fu:
An introduction to CPU and DSP design in China. Sci. China Inf. Sci. 59(1): 1-8 (2016)- 2015
- [c46]Xiaochun Zhang, Qi Guo, Yunji Chen
, Tianshi Chen, Weiwu Hu:
HERMES: a fast cross-ISA binary translator with post-optimization. CGO 2015: 246-256 - 2014
- [j31]Shaoli Liu, Ling Li, Yunji Chen, Weiwu Hu:
Auxiliary stream for optimizing memory access of video decoders. Sci. China Inf. Sci. 57(1): 1-10 (2014) - [j30]Weiwu Hu, Liang Yang, Bao-Xia Fan, Huandong Wang, Yunji Chen:
An 8-Core MIPS-Compatible Processor in 32/28 nm Bulk CMOS. IEEE J. Solid State Circuits 49(1): 41-49 (2014) - [j29]Qi Guo, Tianshi Chen, Yunji Chen, Rui Wang, Huanhuan Chen, Weiwu Hu, Guoliang Chen:
Pre-Silicon Bug Forecast. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(3): 451-463 (2014) - [c45]Hao Li, Shuai Chen, Liqiong Yang, Rui Bai, Weiwu Hu, Freeman Y. Zhong, Samuel Palermo, Patrick Yin Chiang:
A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS. VLSIC 2014: 1-2 - 2013
- [j28]Qi Guo, Tianshi Chen, Yunji Chen, Ling Li, Weiwu Hu:
Microarchitectural design space exploration made fast. Microprocess. Microsystems 37(1): 41-51 (2013) - [j27]Yunji Chen, Tianshi Chen, Ling Li, Ruiyang Wu, Dao-Fu Liu, Weiwu Hu:
Deterministic Replay Using Global Clock. ACM Trans. Archit. Code Optim. 10(1): 1:1-1:28 (2013) - [j26]Yunji Chen, Tianshi Chen, Ling Li, Lei Li, Liang Yang, Menghao Su, Weiwu Hu:
LDet: Determinizing Asynchronous Transfer for Postsilicon Debugging. IEEE Trans. Computers 62(9): 1732-1744 (2013) - [c44]Shuai Chen, Hao Li, Liqiong Yang, Zongren Yang, Weiwu Hu, Patrick Yin Chiang:
A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS. CICC 2013: 1-4 - [c43]Weiwu Hu, Yifu Zhang, Liang Yang, Bao-Xia Fan, Yunji Chen, Shi-Qiang Zhong, Huandong Wang, Zichu Qi, Pengyu Wang, Xiang Gao, Xu Yang, Bin Xiao, Hongsheng Wang, Zongren Yang, Liqiong Yang, Shuai Chen:
Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor. ISSCC 2013: 54-55 - 2012
- [j25]Weiwu Hu, Yunji Chen, Tianshi Chen, Cheng Qian, Lei Li:
Linear Time Memory Consistency Verification. IEEE Trans. Computers 61(4): 502-516 (2012) - [j24]Yunji Chen, Lei Li, Tianshi Chen, Ling Li, Lei Wang, Xiaoxue Feng, Weiwu Hu:
Program Regularization in Memory Consistency Verification. IEEE Trans. Parallel Distributed Syst. 23(11): 2163-2174 (2012) - [c42]Tianshi Chen, Yunji Chen, Qi Guo, Olivier Temam, Yue Wu, Weiwu Hu:
Statistical performance comparisons of computers. HPCA 2012: 399-410 - 2011
- [j23]Zichu Qi, Hui Liu, Xiangku Li, Weiwu Hu:
Design for Testability Features of Godson-3 Multicore Microprocessor. J. Comput. Sci. Technol. 26(2): 302-313 (2011) - [j22]Weiwu Hu, Yan-Ping Gao, Tianshi Chen, Jun-Hua Xiao:
The Godson Processors: Its Research, Development, and Contributions. J. Comput. Sci. Technol. 26(3): 363-372 (2011) - [j21]Ru Wang, Bao-Xia Fan, Liang Yang, Yan-Ping Gao, Dong Liu, Bin Xiao, Jiang-Mei Wang, Yifu Zhang, Hong Wang, Weiwu Hu:
Physical Implementation of the Eight-Core Godson-3B Microprocessor. J. Comput. Sci. Technol. 26(3): 520-527 (2011) - [j20]Ling Li, Yunji Chen, Dao-Fu Liu, Cheng Qian, Weiwu Hu:
An FFT Performance Model for Optimizing General-Purpose Processor Architecture. J. Comput. Sci. Technol. 26(5): 875-889 (2011) - [j19]Rui Bai, Jingguang Wang, Lingli Xia, Feng Zhang, Zongren Yang, Weiwu Hu, Patrick Chiang:
Sinusoidal Clock Sampling for Multigigahertz ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(12): 2808-2815 (2011) - [c41]Qi Guo, Tianshi Chen, Haihua Shen, Yunji Chen, Yue Wu, Weiwu Hu:
Empirical design bugs prediction for verification. DATE 2011: 161-166 - [c40]Yifei Jiang, Mindan Gui, Shuai Chen, Weiwu Hu:
Alpha Compression with Variable Data Formats. Eurographics (Short Papers) 2011: 65-68 - [c39]Qi Guo, Tianshi Chen, Yunji Chen, Zhi-Hua Zhou, Weiwu Hu, Zhiwei Xu:
Effective and Efficient Microprocessor Design Space Exploration Using Unlabeled Design Configurations. IJCAI 2011: 1671-1677 - [c38]Weiwu Hu, Ru Wang, Yunji Chen, Bao-Xia Fan, Shi-Qiang Zhong, Xiang Gao, Zichu Qi, Xu Yang:
Godson-3B: A 1GHz 40W 8-core 128GFLOPS processor in 65nm CMOS. ISSCC 2011: 76-78 - [c37]Lei Li, Tianshi Chen, Yunji Chen, Ling Li, Cheng Qian, Weiwu Hu:
Brief announcement: program regularization in verifying memory consistency. SPAA 2011: 265-266 - 2010
- [j18]Xiang Gao, Yunji Chen, Huandong Wang, Dan Tang, Weiwu Hu:
System Architecture of Godson-3 Multi-Core Processors. J. Comput. Sci. Technol. 25(2): 181-191 (2010) - [c36]Qi Guo, Tianshi Chen, Haihua Shen, Yunji Chen, Weiwu Hu:
On-the-Fly Reduction of Stimuli for Functional Verification. Asian Test Symposium 2010: 448-454 - [c35]Huandong Wang, Xiang Gao, Yunji Chen, Dan Tang, Weiwu Hu:
A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only). FPGA 2010: 283 - [c34]Dan Tang, Yungang Bao, Weiwu Hu, Mingyu Chen:
DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance. HPCA 2010: 1-12 - [c33]Yunji Chen, Weiwu Hu, Tianshi Chen, Ruiyang Wu:
LReplay: a pending period based deterministic replay scheme. ISCA 2010: 187-197 - [c32]Jun Xu, Ge Zhang, Weiwu Hu:
Optimizing power and throughput for m-out-of-n encoded asynchronous circuits. ISQED 2010: 151-157 - [c31]Zichu Qi, Qi Guo, Ge Zhang, Xiangku Li, Weiwu Hu:
Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power. VLSI Design 2010: 206-211
2000 – 2009
- 2009
- [j17]Weiwu Hu, Jian Wang, Xiang Gao, Yunji Chen, Qi Liu, Guojie Li:
Godson-3: A Scalable Multicore RISC Processor with x86 Emulation. IEEE Micro 29(2): 17-29 (2009) - [c30]Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu:
A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. Asian Test Symposium 2009: 219-224 - [c29]Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen, Haihua Shen, Pengyu Wang, Hong Pan:
Fast complete memory consistency verification. HPCA 2009: 381-392 - [c28]Weiwu Hu, Qi Liu, Jian Wang, Songsong Cai, Menghao Su, Xiaoyu Li:
Efficient binary translation system with low hardware cost. ICCD 2009: 305-312 - [c27]Zichu Qi, Hui Liu, Xiangku Li, Jun Xu, Weiwu Hu:
A case study of improving at-speed testing coverage of a gigahertz microprocessor. ICECS 2009: 651-654 - [c26]Zhuo Gao, D. Kesharwani, Patrick Chiang, Weiwu Hu:
Measuring and Compensating for Process Mismatch-induced, Reference Spurs in Phase-locked Loops using a Sub-sampled DSP. ISCAS 2009: 1585-1588 - [i1]Yunji Chen, Tianshi Chen, Weiwu Hu:
Global Clock, Physical Time Order and Pending Period Analysis in Multiprocessor Systems. CoRR abs/0903.4961 (2009) - 2008
- [j16]Zusong Li, Dandan Huan, Weiwu Hu, Zhimin Tang:
Chip Multithreaded Consistency Model. J. Comput. Sci. Technol. 23(2): 298-305 (2008) - [j15]Weiwu Hu, Jian Wang:
Making Effective Decisions in Computer Architects' Real-World: Lessons and Experiences with Godson-2 Processor Designs. J. Comput. Sci. Technol. 23(4): 620-632 (2008) - [c25]Feng Zhang, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu:
A High Speed CMOS Transmitter and Rail-to-Rail Receiver. DELTA 2008: 67-70 - [c24]Lin Ma, Yunji Chen, Menghao Su, Zichu Qi, Heng Zhang, Weiwu Hu:
Testing content addressable memories using instructions and march-like algorithms. ICECS 2008: 774-777 - [c23]Hongbo Zeng, Jun Wang, Ge Zhang, Weiwu Hu:
An interconnect-aware power efficient cache coherence protocol for CMPs. IPDPS 2008: 1-11 - [c22]Qifei Fan, Ge Zhang, Weiwu Hu:
A synchronized variable frequency clock scheme in chip multiprocessors. ISCAS 2008: 3410-3413 - [c21]Shijian Zhang, Weiwu Hu:
Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor. PRDC 2008: 1-8 - 2007
- [j14]Weiwu Hu, Ji-Ye Zhao, Shi-Qiang Zhong, Xu Yang, Elio Guidetti, Chris Wu:
Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology. J. Comput. Sci. Technol. 22(1): 1-14 (2007) - [j13]Hou Rui, Longbing Zhang, Weiwu Hu:
Accelerating sequential programs on Chip Multiprocessors via Dynamic Prefetching Thread. Microprocess. Microsystems 31(3): 200-211 (2007) - [c20]Hongbo Zeng, Kun Huang, Ming Wu, Weiwu Hu:
Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs. Asia-Pacific Computer Systems Architecture Conference 2007: 304-314 - [c19]Shijian Zhang, Weiwu Hu:
CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors. ATS 2007: 313-318 - [c18]Jun Wang, Ge Zhang, Weiwu Hu:
An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects. ISCAS 2007: 3712-3715 - 2006
- [j12]Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang:
High Performance General-Purpose Microprocessors: Past and Future. J. Comput. Sci. Technol. 21(5): 631-640 (2006) - [j11]Ge Zhang, Weiwu Hu, Zichu Qi:
Parallel Error Detection for Leading Zero Anticipation. J. Comput. Sci. Technol. 21(6): 901-906 (2006) - [c17]Dandan Huan, Zusong Li, Weiwu Hu, Zhiyong Liu:
Processor Directed Dynamic Page Policy. Asia-Pacific Computer Systems Architecture Conference 2006: 109-122 - [c16]Hou Rui, Longbing Zhang, Weiwu Hu:
A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors. Euro-Par 2006: 506-516 - [c15]Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang:
Microarchitecture and Performance Analysis of Godson-2 SMT Processor. ICCD 2006: 485-490 - 2005
- [j10]Weiwu Hu, Fuxin Zhang, Zusong Li:
Microarchitecture of the Godson-2 Processor. J. Comput. Sci. Technol. 20(2): 243-249 (2005) - [c14]Hou Rui, Fuxin Zhang, Weiwu Hu:
A Memory Bandwidth Effective Cache Store Miss Policy. Asia-Pacific Computer Systems Architecture Conference 2005: 750-760 - [c13]Ge Zhang, Zichu Qi, Weiwu Hu:
A novel design of leading zero anticipation circuit with parallel error detection. ISCAS (1) 2005: 676-679 - 2004
- [c12]Gang Shi, Mingchang Hu, Hongda Yin, Weiwu Hu, Zhimin Tang:
A shared virtual memory network with fast remote direct memory access and message passing. CLUSTER 2004: 495 - 2001
- [j9]Weiwu Hu, Weisong Shi, Zhimin Tang:
Optimizing Home-Based Software DSM Protocols. Clust. Comput. 4(3): 235-242 (2001) - [j8]Weiwu Hu, Fuxin Zhang, Haiming Liu:
Dynamic Data Prefetching in Home-Based Software DSMs. J. Comput. Sci. Technol. 16(3): 231-241 (2001) - [c11]Weiwu Hu, Gang Shi, Fuxin Zhang:
Communication with Threads in Software DSM. CLUSTER 2001: 149-154 - [c10]Haiming Liu, Weiwu Hu:
A Comparison of Two Strategies of Dynamic Data Prefetching in Software DSM. IPDPS 2001: 62 - 2000
- [c9]Weiwu Hu, Fuxin Zhang, Haiming Liu:
A New Home-Based Software DSM Protocol for SMP Clusters. Euro-Par 2000: 1132-1142
1990 – 1999
- 1999
- [j7]Weisong Shi, Weiwu Hu, Zhimin Tang:
Where does the time go in software DSMs? - Experiences with JIAJIA. J. Comput. Sci. Technol. 14(3): 193-205 (1999) - [c8]Weiwu Hu, Weisong Shi, Zhimin Tang:
Write Detection in Home-Based Software DSMs. Euro-Par 1999: 909-913 - [c7]M. Rasit Eskicioglu, T. Anthony Marsland, Weiwu Hu, Weisong Shi:
Evaluation of the JIAJIA Software DSM System on High Performance Computer Architectures. HICSS 1999 - [c6]Weiwu Hu, Weisong Shi, Zhimin Tang:
JIAJIA: A Software DSM System Based on a New Cache Coherence Protocol. HPCN Europe 1999: 463-472 - [c5]Weisong Shi, Weiwu Hu, Zhimin Tang, M. Rasit Eskicioglu:
Dynamic Task Migration in Home-based Software DSM Systems. HPDC 1999: 339-340 - [c4]Weiwu Hu, Weisong Shi, Zhimin Tang:
Adaptive Write Detection in Home-based Software DSMs. HPDC 1999: 353-354 - [c3]Weiwu Hu, Weisong Shi, Zhimin Tang:
Reducing System Overheads in Home-based Software DSMs. IPPS/SPDP 1999: 167-173 - 1998
- [j6]Weiwu Hu, Weisong Shi, Zhimin Tang, Ming Li:
A lock-based cache coherence protocol for scope consistency. J. Comput. Sci. Technol. 13(2): 97-109 (1998) - [j5]Weiwu Hu, Weisong Shi, Zhimin Tang:
A framework of memory consistency models. J. Comput. Sci. Technol. 13(2): 110-124 (1998) - [j4]Weiwu Hu, Peisu Xia:
Out-of-order execution in sequentially consistent shared-memory systems: Theory and experiments. J. Comput. Sci. Technol. 13(2): 125-140 (1998) - 1997
- [j3]Weiwu Hu, Peisu Xia:
Out-of-order execution in sequentially consistent shared-memory systems. SIGARCH Comput. Archit. News 25(4): 3-10 (1997) - [j2]Weisong Shi, Weiwu Hu, Ming Zhu:
An innovative implementation for directory-based cache coherence in shared memory multiprocessors. SIGARCH Comput. Archit. News 25(5): 2-9 (1997) - [j1]Weisong Shi, Weiwu Hu, Zhimin Tang:
An Interaction of Coherence Protocols and Memory Consistency Models in DSM Systems. ACM SIGOPS Oper. Syst. Rev. 31(4): 41-54 (1997) - 1996
- [c2]Weiwu Hu, Peisu Xia:
Event Ordering Condition for Correct Executions in Shared-Memory Systems. ISPAN 1996: 84-89 - 1994
- [c1]Weiwu Hu:
A Graph Model for Investigating Memory Consistency. ICPADS 1994: 516-523
Coauthor Index
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