default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDZeljko Zilic
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j53]Ghassan Al-Sumaidaee
, Zeljko Zilic:
Sensing Data Concealment in NFTs: A Steganographic Model for Confidential Cross-Border Information Exchange. Sensors 24(4): 1264 (2024)- [j52]Reza Amini Gougeh, Zeljko Zilic:
Systematic Review of IoT-Based Solutions for User Tracking: Towards Smarter Lifestyle, Wellness and Health Management. Sensors 24(18): 5939 (2024) - [c140]Miguel Angel Alfaro Zapata, Amirhossein Shahshahani, Zeljko Zilic:
Automated Assertion Checker Generator and Information Flow Tracking for Security Verification. ISQED 2024: 1-6 - [c139]Reza Amini Gougeh, Nu Zhang, Zeljko Zilic:
Optimizing Auditory Immersion Safety on Edge Devices: An On-Device Sound Event Detection System. Odyssey 2024: 225-231 - 2023
- [j51]Anastasios Alexandridis, Ghassan Al-Sumaidaee, Zeljko Zilic, Gwanggil Jeon, Junchao Wang:
An IoT Ecosystem Platform for the Evaluation of Blockchain Feasibility. IEEE Internet Things J. 10(24): 21515-21527 (2023) - [j50]Ghassan Al-Sumaidaee, Rami Alkhudary, Zeljko Zilic, Andraws I. Swidan:
Performance analysis of a private blockchain network built on Hyperledger Fabric for healthcare. Inf. Process. Manag. 60(2): 103160 (2023) - [j49]Garrett Kinman, Zeljko Zilic, David Purnell:
Scheduling Sparse LEO Satellite Transmissions for Remote Water Level Monitoring. Sensors 23(12): 5581 (2023) - [c138]Ghassan Al-Sumaidaee, Rami Alkhudary, Zeljko Zilic, Andraws I. Swidan:
An Evaluation Framework for Assessing IPFS Performance within a Blockchain-Based Healthcare System. Blockchain 2023: 100-104 - [c137]Ghassan Al-Sumaidaee, Rami Alkhudary, Zeljko Zilic:
Non-Fungible Tokens (NFTs) as a Means for Blockchain Networks Integration in Healthcare. BRAINS 2023: 1-2 - [c136]Xiangyun Wang, Yicheng Song, Katyayani Prakash, Zeljko Zilic, Tomas Langsetmo:
Quality-driven Design Methodology for PUFs in FPGAs for Secure IoT. ISQED 2023: 1-8 - 2022
- [j48]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Wearable Vibrotactile System as an Assistive Technology Solution. Mob. Networks Appl. 27(2): 709-717 (2022) - [c135]Ghassan Al-Sumaidaee, Anastasios Alexandridis, Rami Alkhudary, Zeljko Zilic:
A Technical Assessment of Blockchain in Healthcare with a Focus on Big Data. IEEE Big Data 2022: 2467-2472 - [c134]Anastasios Alexandridis, Ghassan Al-Sumaidaee, Rami Alkhudary, Zeljko Zilic:
A Stylized Presence Detection System in the Era of Blockchain and Big Data. IEEE Big Data 2022: 6575-6577 - [c133]Ghassan Al-Sumaidaee, Rami Alkhudary, Zeljko Zilic:
Decentralized Storage for Big Data in Healthcare between Reality and Ambition: IPFS and Sia. IEEE Big Data 2022: 6578-6580 - [c132]Mian Hamza, Sharmistha Bhadra, Zeljko Zilic:
Sleep Stage Detection on a Wearable Headband Using Deep Neural Networks. GIOTS 2022: 187-198 - [c131]Farimah Poursafaei, Zeljko Zilic, Reihaneh Rabbany:
A Strong Node Classification Baseline for Temporal Graphs. SDM 2022: 648-656 - 2021
- [j47]Junchao Wang, Shengwen Fan, Anastasios Alexandridis, Kaining Han, Gwanggil Jeon, Zeljko Zilic, Yu Pang:
A Multistage Blockchain-Based Secure and Trustworthy Smart Healthcare System Using ECG Characteristic. IEEE Internet Things Mag. 4(3): 48-58 (2021) - [c130]Anastasios Alexandridis, Ghassan Al-Sumaidaee, Rami Alkhudary, Zeljko Zilic:
Making Case for Using RAFT in Healthcare Through Hyperledger Fabric. IEEE BigData 2021: 2185-2191 - [c129]Farimah Poursafaei, Reihaneh Rabbany, Zeljko Zilic:
SigTran: Signature Vectors for Detecting Illicit Activities in Blockchain Transaction Networks. PAKDD (1) 2021: 27-39 - [i2]Pavel Sinha, Ioannis N. Psaromiligkos, Zeljko Zilic:
A Structurally Regularized Convolutional Neural Network for Image Classification using Wavelet-based SubBand Decomposition. CoRR abs/2103.01823 (2021) - 2020
- [j46]Junchao Wang, Kaining Han, Anastasios Alexandridis, Zhiyu Chen, Zeljko Zilic, Yu Pang, Gwanggil Jeon, Francesco Piccialli:
A blockchain-based eHealthcare system interoperating with WBANs. Future Gener. Comput. Syst. 110: 675-685 (2020) - [j45]Amirhossein Shahshahani, Zeljko Zilic, Sharmistha Bhadra:
An Ultrasound-Based Biomedical System for Continuous Cardiopulmonary Monitoring: A Single Sensor for Multiple Information. IEEE Trans. Biomed. Eng. 67(1): 268-276 (2020) - [j44]Ashraf Suyyagh, Zeljko Zilic:
Energy and Task-Aware Partitioning on Single-ISA Clustered Heterogeneous Processors. IEEE Trans. Parallel Distributed Syst. 31(2): 306-317 (2020) - [c128]Farimah Poursafaei, Ghaith Bany Hamad, Zeljko Zilic:
Detecting Malicious Ethereum Entities via Application of Machine Learning Classification. BRAINS 2020: 120-127 - [c127]Pavel Sinha, Yimeng Wu, Ioannis N. Psaromiligkos, Zeljko Zilic:
Lumen & Media Segmentation of IVUS Images via Ellipse Fitting Using a Wavelet-Decomposed Subband CNN. MLSP 2020: 1-6
2010 – 2019
- 2019
- [j43]Junchao Wang, Kaining Han, Anastasios Alexandridis, Zeljko Zilic, Jinzhao Lin, Yu Pang, Xiaomin Yang:
A baseband processing ASIC for body area networks. J. Ambient Intell. Humaniz. Comput. 10(10): 3975-3982 (2019) - [c126]Pavel Sinha, Ioannis N. Psaromiligkos, Zeljko Zilic:
A Structurally Regularized Convolutional Neural Network for Image Classification Using Wavelet-Based Subband Decomposition. ICIP 2019: 649-653 - [c125]Jianing Sun, Katarzyna Radecka, Zeljko Zilic:
Exploring Better Food Detection via Transfer Learning. MVA 2019: 1-6 - [p1]Liangguang Peng, Jinzhao Lin, Tong Bai, Yu Pang, Guoquan Li, Huiquan Wang, Xiaoming Jiang, Junchao Wang, Zeljko Zilic:
An Encryption Method for BAN Using the Channel Characteristics. Advances in Body Area Networks I 2019: 221-233 - [i1]Jianing Sun, Katarzyna Radecka, Zeljko Zilic:
FoodTracker: A Real-time Food Detection Mobile Application by Deep Convolutional Neural Networks. CoRR abs/1909.05994 (2019) - 2018
- [j42]Ravdeep Singh Boparai, Anastasios Alexandridis, Zeljko Zilic:
Multi-point Security by a Multiplatform-compatible Multifunctional Authentication and Encryption Board. J. Comput. Inf. Technol. 26(4): 235-250 (2018) - [j41]Junchao Wang, Kaining Han, Anastasios Alexandridis, Zeljko Zilic, Yu Pang, Wei Wu, Sadia Din, Gwanggil Jeon:
A novel security scheme for Body Area Networks compatible with smart vehicles. Comput. Networks 143: 74-81 (2018) - [j40]Tong Bai, Jinzhao Lin, Yu Pang, Guoquan Li, Zhangyong Li, Huiqian Wang, Junchao Wang, Zeljko Zilic:
Protocol with self-adaptive GB for BANs. IET Commun. 12(9): 1042-1047 (2018) - [j39]Amirhossein Shahshahani, Carl Laverdiere, Sharmistha Bhadra, Zeljko Zilic:
Ultrasound Sensors for Diaphragm Motion Tracking: An Application in Non-Invasive Respiratory Monitoring. Sensors 18(8): 2617 (2018) - [j38]Junchao Wang, Kaining Han, Zhiyu Chen, Anastasios Alexandridis, Zeljko Zilic, Yu Pang, Jinzhao Lin:
A Software Defined Radio Evaluation Platform for WBAN Systems. Sensors 18(12): 4494 (2018) - [c124]Zhiyu Chen, Junchao Wang, Kaining Han, Zeljko Zilic:
Software Defined Radio-Based Testbed for Wireless Body Area Network. BIBE 2018: 221-224 - [c123]Anant Kulkarni, Brajesh Kumar Kaushik, Zeljko Zilic:
Implementation and Analysis of Spin-Torque-Based Reversible D-Latch. CCECE 2018: 1-4 - [c122]Amirhossein Shahshahani, Sharmistha Bhadra, Zeljko Zilic:
Ultrasound Based Respiratory Monitoring Evaluation Under Human Body Motions. IEEE SENSORS 2018: 1-4 - [c121]Amirhossein Shahshahani, Sharmistha Bhadra, Zeljko Zilic:
A Continuous Respiratory Monitoring System Using Ultrasound Piezo Transducer. ISCAS 2018: 1-4 - [c120]Junchao Wang, Kaining Han, Anastasios Alexandridis, Zeljko Zilic, Yu Pang, Jinzhao Lin:
An ASIC Implementation of Security Scheme for Body Area Networks. ISCAS 2018: 1-5 - [c119]Junchao Wang, Kaining Han, Anastasios Alexandridis, Zeljko Zilic, Tong Bai, Jinzhao Lin, Yu Pang, Guoquan Li:
Using the Characteristic Value of the Body Channel for Encryption of Body Area Networks. NEWCAS 2018: 265-268 - [c118]Sanjay Prajapati, Zeljko Zilic, Brajesh Kumar Kaushik:
Area and Energy Efficient Magnetic Full Adder based on Differential Spin Hall MRAM. NEWCAS 2018: 317-321 - 2017
- [j37]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
A Comprehensive Analysis on Wearable Acceleration Sensors in Human Activity Recognition. Sensors 17(3): 529 (2017) - [c117]Junchao Wang, Zeljko Zilic, Yutian Shu:
Evaluation of an RF wearable device for non-invasive real-time hydration monitoring. BSN 2017: 91-94 - [c116]Andrey Tolstikhin, Zeljko Zilic:
Concealed regression for aggregation in low power wireless networks. ICIN 2017: 260-267 - [c115]Amirhossein Shahshahani, Davood Raeisi Nafchi, Zeljko Zilic:
Ultrasound sensors and its application in human heart rate monitoring. ISCAS 2017: 1-4 - [c114]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Designing and Evaluating a Vibrotactile Language for Sensory Substitution Systems. MobiHealth 2017: 58-66 - [c113]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
A Novel Algorithm to Reduce Machine Learning Efforts in Real-Time Sensor Data Analysis. MobiHealth 2017: 83-90 - 2016
- [j36]Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
Respiration Disorders Classification With Informative Features for m-Health Applications. IEEE J. Biomed. Health Informatics 20(3): 733-747 (2016) - [c112]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Haptic feedback and human performance in a wearable sensor system. BHI 2016: 620-624 - [c111]Yi Steven Ding, Zeljko Zilic:
ECG compression for mobile sensor platforms. BSN 2016: 99-104 - [c110]Andraws I. Swidan, Haytham Bani Abdelghany, Ramzi R. Saifan, Zeljko Zilic:
Mobility and Direction Aware Ad-hoc on Demand Distance Vector Routing Protocol. FNC/MobiSPC 2016: 49-56 - [c109]Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic:
Capturing True Workload Dependency of BTI-induced Degradation in CPU Components. ACM Great Lakes Symposium on VLSI 2016: 373-376 - [c108]Jason G. Tong, Marc Boule, Zeljko Zilic:
Accelerating assertion assessment using GPUs. HLDVT 2016: 9-16 - [c107]Amirhossein Shahshahani, Andrey Tolstikhin, Zeljko Zilic:
Enabling Debug in IoT Wireless Development and Deployment with Security Considerations. NATW 2016: 53-58 - [c106]Ari J. G. Ramdial, Zeljko Zilic:
Design of a modeling and validation platform for closed loop glucose control. SummerSim 2016: 42 - [c105]Ari J. G. Ramdial, Zeljko Zilic:
Adaptive parametric tuning of glucose-insulin kinetics models using multilayer perceptrons. SummerSim 2016: 43 - 2015
- [j35]Mohammad Hossein Neishaburi, Zeljko Zilic:
System on chip failure rate assessment using the executable model of a system. Computing 97(6): 611-629 (2015) - [j34]Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
Movement analysis of the chest compartments and a real-time quality feedback during breathing therapy. Netw. Model. Anal. Health Informatics Bioinform. 4(1): 21 (2015) - [j33]Bojan Mihajlovic, Zeljko Zilic, Warren J. Gross:
Architecture-Aware Real-Time Compression of Execution Traces. ACM Trans. Embed. Comput. Syst. 14(4): 75:1-75:24 (2015) - [j32]Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Design and Evaluation of an Intelligent Remote Tidal Volume Variability Monitoring System in E-Health Applications. IEEE J. Biomed. Health Informatics 19(5): 1532-1548 (2015) - [c104]Benjamin Nahill, Zeljko Zilic:
FLogFS: A lightweight flash log file system. BSN 2015: 1-6 - [c103]Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic:
Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models. ACM Great Lakes Symposium on VLSI 2015: 57-62 - 2014
- [j31]Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
A Medical Cloud-Based Platform for Respiration Rate Measurement and Hierarchical Classification of Breath Disorders. Sensors 14(6): 11204-11224 (2014) - [j30]Mohammad Hossein Neishaburi, Zeljko Zilic:
On a New Mechanism of Trigger Generation for Post-Silicon Debugging. IEEE Trans. Computers 63(9): 2330-2342 (2014) - [j29]Bojan Mihajlovic, Zeljko Zilic, Warren J. Gross:
Dynamically Instrumenting the QEMU Emulator for Linux Process Trace Generation with the GDB Debugger. ACM Trans. Embed. Comput. Syst. 13(5s): 167:1-167:18 (2014) - [c102]Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Design of an e-Health Respiration and Body Posture Monitoring System and Its Application for Rib Cage and Abdomen Synchrony Analysis. BIBE 2014: 141-148 - [c101]Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Zeljko Zilic:
Linear regression techniques for efficient analysis of transistor variability. ICECS 2014: 267-270 - [c100]Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
Multi-sensor blind recalibration in mHealth applications. IHTC 2014: 1-4 - [c99]Majid Janidarmian, Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Affordable erehabilitation monitoring platform. IHTC 2014: 1-6 - [c98]Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
Development of a Remote Monitoring System for Respiratory Analysis. IoT360 (1) 2014: 193-202 - [c97]Atena Roshan Fekr, Katarzyna Radecka, Zeljko Zilic:
Tidal volume variability and respiration rate estimation using a wearable accelerometer sensor. MobiHealth 2014: 1-6 - [c96]Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic:
Automated diagnosis of knee pathology using sensory data. MobiHealth 2014: 95-98 - [c95]Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic:
A hybrid arithmetic transform for precision analysis of floating-point polynomial specifications. NEWCAS 2014: 37-40 - 2013
- [j28]Mohammad Hossein Neishaburi, Zeljko Zilic:
A Fault Tolerant Hierarchical Network on Chip Router Architecture. J. Electron. Test. 29(4): 485-497 (2013) - [j27]Mohammad Hossein Neishaburi, Zeljko Zilic:
NISHA: A fault-tolerant NoC router enabling deadlock-free Interconnection of Subnets in Hierarchical Architectures. J. Syst. Archit. 59(7): 551-569 (2013) - [j26]Zeljko Zilic:
"Quantum Circuit Simulations" by G. F. Viamontes, I. L. Markov and J. P. Hayes. Quantum Inf. Process. 12(4): 1831-1833 (2013) - [j25]Jason G. Tong, Marc Boule, Zeljko Zilic:
Test compaction techniques for assertion-based test generation. ACM Trans. Design Autom. Electr. Syst. 19(1): 9:1-9:29 (2013) - [c94]Yu Pang, Qian Lei, Jinzhao Lin, Zhiyong Luo, Zhangyong Li, Zeljko Zilic, Katarzyna Radecka:
SAR Computation and Channel Modeling of Body Area Network. BODYNETS 2013: 120-123 - [c93]Omid Sarbishei, Benjamin Nahill, Atena Roshan Fekr, Majid Janidarmian, Katarzyna Radecka, Zeljko Zilic, Boris Karajica:
An efficient fault-tolerant sensor fusion algorithm for accelerometers. BSN 2013: 1-6 - [c92]Zeljko Zilic:
Tutorial: Methodologies and tools for embedded multisensory systems based on ARM cortex M processors. CASES 2013: 1-8 - [c91]Benjamin Nahill, Ari Ramdial, Haibo Zeng, Marco Di Natale, Zeljko Zilic:
An FPGA implementation of wait-free data synchronization protocols. ETFA 2013: 1-8 - [c90]Jason G. Tong, Marc Boule, Zeljko Zilic:
Efficient Data Encoding for Improving Fault Simulation Performance on GPUs. ISED 2013: 138-142 - [c89]Ashraf Suyyagh, Benjamin Nahill, Alexandre Courtemanche, Evgeny Kirshin, Zeljko Zilic, Boris Karajica:
Managing the microprocessor course scope expansion. MSE 2013: 36-39 - 2012
- [j24]Mohammad Hossein Neishaburi, Zeljko Zilic:
An infrastructure for debug using clusters of assertion-checkers. Microelectron. Reliab. 52(11): 2781-2798 (2012) - [j23]Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic:
Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 343-355 (2012) - [j22]Atanu Chattopadhyay, Zeljko Zilic:
Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 523-536 (2012) - [c88]Atena Roshan Fekr, Majid Janidarmian, Omid Sarbishei, Benjamin Nahill, Katarzyna Radecka, Zeljko Zilic:
MSE minimization and fault-tolerant data fusion for multi-sensor systems. ICCD 2012: 445-452 - [c87]Majid Janidarmian, Zeljko Zilic, Katarzyna Radecka:
Issues in Multi-valued Multi-modal Sensor Fusion. ISMVL 2012: 238-243 - [c86]Jason G. Tong, Marc Bottle, Zeljko Zilic:
Assertion clustering for compacted test sequence generation. ISQED 2012: 694-701 - [c85]Mohammad Hossein Neishaburi, Zeljko Zilic:
An enhanced debug-aware network interface for Network-on-Chip. ISQED 2012: 709-716 - [c84]Luca Montesi, Zeljko Zilic, Takahiro Hanyu, Daisuke Suzuki:
Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs. ISVLSI 2012: 302-307 - [c83]Rozita Najafi, Carle Banville, Mohamed Hafed, Zeljko Zilic:
Oversampled multi-phase time-domain bit-error rate processing for transmitter testing. NEWCAS 2012: 181-184 - [c82]Edin Kadric, Naraig Manjikian, Zeljko Zilic:
An FPGA implementation for a high-speed optical link with a PCIe interface. SoCC 2012: 83-87 - 2011
- [j21]Prabhat Mishra, Zeljko Zilic, Sandeep K. Shukla:
Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models. IEEE Des. Test Comput. 28(3): 6-9 (2011) - [j20]Zeljko Zilic, Prabhat Mishra, Sandeep K. Shukla:
Challenges of Rapidly Emerging Consumer Space Multiprocessors. IEEE Des. Test Comput. 28(3): 52-53 (2011) - [j19]Sandeep K. Shukla, Prabhat Mishra, Zeljko Zilic:
A Brief History of Multiprocessors and EDA. IEEE Des. Test Comput. 28(3): 96 (2011) - [j18]Stephan Bourduas, Zeljko Zilic:
Modeling and evaluation of ring-based interconnects for Network-on-Chip. J. Syst. Archit. 57(1): 39-60 (2011) - [c81]Yu Pang, Katarzyna Radecka, Zeljko Zilic:
An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. ASP-DAC 2011: 455-460 - [c80]Mohammad Hossein Neishaburi, Zeljko Zilic:
Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis. DFT 2011: 120-128 - [c79]Mohammad Hossein Neishaburi, Zeljko Zilic:
Debug Aware AXI-based Network Interface. DFT 2011: 399-407 - [c78]Mohammad Hossein Neishaburi, Zeljko Zilic:
A Fault Tolerant Hierarchical Network on Chip Router Architecture. DFT 2011: 445-453 - [c77]Mohammad Hossein Neishaburi, Zeljko Zilic:
On Failure Rate Assessment Using an Executable Model of the System. DSD 2011: 29-36 - [c76]Bojan Mihajlovic, Zeljko Zilic:
Real-time address trace compression for emulated and real system-on-chip processor core debugging. ACM Great Lakes Symposium on VLSI 2011: 331-336 - [c75]Mohammad Hossein Neishaburi, Zeljko Zilic:
ERAVC: Enhanced reliability aware NoC router. ISQED 2011: 591-596 - [c74]Zeljko Zilic, Boris Karajica:
Teaching for evolution towards embedded multi-sensor interfaces. MSE 2011: 1-4 - [c73]Zeljko Zilic, Boris Karajica:
High-level design of integrated microsystems - arithmetic perspective. ROSE 2011: 77-82 - [c72]Mohammad Hossein Neishaburi, Zeljko Zilic:
A distributed AXI-based platform for post-silicon validation. VTS 2011: 8-13 - [c71]Zeljko Zilic, Katarzyna Radecka:
Fault tolerant glucose sensor readout and recalibration. Wireless Health 2011: 35 - [e1]Zeljko Zilic, Sandeep K. Shukla:
2011 IEEE International High Level Design Validation and Test Workshop, HLDVT 2011, Napa Valley, CA, USA, November 9-11, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1744-4 [contents] - 2010
- [j17]Yongquan Fan, Zeljko Zilic:
Qualifying Serial Interface Jitter Rapidly and Cost-effectively. J. Electron. Test. 26(2): 177-193 (2010) - [j16]Jason G. Tong, Marc Boule, Zeljko Zilic:
Defining and Providing Coverage for Assertion-Based Dynamic Verification. J. Electron. Test. 26(2): 211-225 (2010) - [j15]Yu Pang, Katarzyna Radecka, Zeljko Zilic:
Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1177-1190 (2010) - [j14]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic:
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1436-1448 (2010) - [c70]Mohammad Hossein Neishaburi, Zeljko Zilic:
Enabling efficient post-silicon debug by clustering of hardware-assertions. DATE 2010: 985-988 - [c69]Omar Abdelfattah, Andraws I. Swidan, Zeljko Zilic:
Direct residue-to-analog conversion scheme based on Chinese Remainder Theorem. ICECS 2010: 687-690 - [c68]Yu Pang, Katarzyna Radecka, Zeljko Zilic:
An efficient method to perform range analysis for DSP circuits. ICECS 2010: 855-858
2000 – 2009
- 2009
- [c67]Ivan Bilicki, Vijay Sundaresan, Daryl Maier, Nikola Grcevski, Zeljko Zilic:
Cache line reservation: exploring a scheme for cache-friendly object allocation. CASCON 2009: 247-260 - [c66]Atanu Chattopadhyay, Zeljko Zilic:
Serial reconfigurable mismatch-tolerant clock distribution. DAC 2009: 611-612 - [c65]Yann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic:
MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI 2009: 75-80 - [c64]Mohammad Hossein Neishaburi, Zeljko Zilic:
Reliability aware NoC router architecture using input channel buffer sharing. ACM Great Lakes Symposium on VLSI 2009: 511-516 - [c63]Jason G. Tong, Marc Boule, Zeljko Zilic:
Airwolf-TG: A test generator for assertion-based dynamic verification. HLDVT 2009: 106-113 - [c62]Yongquan Fan, Zeljko Zilic:
A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces. HLDVT 2009: 114-121 - [c61]Zeljko Zilic:
Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age. ISMVL 2009: 268-273 - [c60]Yongquan Fan, Zeljko Zilic:
Accelerating jitter tolerance qualification for high speed serial interfaces. ISQED 2009: 360-365 - 2008
- [j13]Stephan Bourduas, Jean-Samuel Chenard, Zeljko Zilic:
A Quality-Driven Design Approach for NoCs. IEEE Des. Test Comput. 25(5): 416-428 (2008) - [j12]Jean-Samuel Chenard, Zeljko Zilic, Milos Prokic:
A Laboratory Setup and Teaching Methodology for Wireless and Mobile Embedded Systems. IEEE Trans. Educ. 51(3): 378-384 (2008) - [j11]Yongquan Fan, Zeljko Zilic:
BER Testing of Communication Interfaces. IEEE Trans. Instrum. Meas. 57(5): 897-906 (2008) - [j10]Marc Boule, Zeljko Zilic:
Automata-based assertion-checker synthesis of PSL properties. ACM Trans. Design Autom. Electr. Syst. 13(1): 4:1-4:21 (2008) - [c59]Atanu Chattopadhyay, Zeljko Zilic:
Built-in Clock Skew System for On-line Debug and Repair. DATE 2008: 248-251 - [c58]Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic:
Proving and disproving assertion rewrite rules with automated theorem provers. HLDVT 2008: 56-63 - 2007
- [j9]Marc Boule, Jean-Samuel Chenard, Zeljko Zilic:
Debug enhancements in assertion-checker generation. IET Comput. Digit. Tech. 1(6): 669-677 (2007) - [j8]Zeljko Zilic, Katarzyna Radecka:
Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. IEEE Trans. Computers 56(2): 202-207 (2007) - [c57]Stephan Bourduas, Zeljko Zilic:
Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing. ASAP 2007: 302-307 - [c56]Marc Boule, Zeljko Zilic:
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. ASP-DAC 2007: 324-329 - [c55]Henry H. Y. Chan, Zeljko Zilic:
Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. DAC 2007: 430-435 - [c54]Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur:
Reversible circuit technology mapping from non-reversible specifications. DATE 2007: 558-563 - [c53]Atanu Chattopadhyay, Zeljko Zilic:
Reconfigurable Clock Distribution Circuitry. ISCAS 2007: 877-880 - [c52]Henry H. Y. Chan, Zeljko Zilic:
A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits. ISCAS 2007: 2934-2937 - [c51]Marc Boule, Jean-Samuel Chenard, Zeljko Zilic:
Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. ISQED 2007: 613-620 - [c50]Yongquan Fan, Yi Cai, Zeljko Zilic:
A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata. ITC 2007: 1-10 - [c49]Zeljko Zilic, Jean-Samuel Chenard, Milos Prokic:
A Laboratory for Wireless and Mobile Embedded Systems. MSE 2007: 103-104 - [c48]Stephan Bourduas, Zeljko Zilic:
A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing. NOCS 2007: 195-204 - 2006
- [j7]Knockaert Radecka, Zeljko Zilic:
Arithmetic transforms for compositions of sequential and imprecise datapaths. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1382-1391 (2006) - [c47]Marc Boule, Zeljko Zilic:
Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties. HLDVT 2006: 69-76 - [c46]Marc Boule, Jean-Samuel Chenard, Zeljko Zilic:
Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. ICCD 2006: 294-299 - [c45]Yu Pang, Katarzyna Radecka, Zeljko Zilic:
Algorithms for Compositions of Arithmetic Transforms and Their Extensions. ICECS 2006: 379-382 - [c44]Yu Pang, Katarzyna Radecka, Zeljko Zilic:
Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion. ICECS 2006: 696-699 - [c43]Yongquan Fan, Yi Cai, Liming Fang, Anant Verma, William Burchanowski, Zeljko Zilic, Sandeep Kumar:
An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA. ITC 2006: 1-10 - [c42]Rong Zhang, Zeljko Zilic, Katarzyna Radecka:
Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. VTS 2006: 186-191 - 2005
- [j6]Atanu Chattopadhyay, Zeljko Zilic:
GALDS: a complete framework for designing multiclock ASICs and SoCs. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 641-654 (2005) - [c41]Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic:
Design methodology for wireless nodes with printed antennas. DAC 2005: 291-296 - [c40]Marc Boule, Zeljko Zilic:
Incorporating Ef.cient Assertion Checkers into Hardware Emulation. ICCD 2005: 221-228 - [c39]Henry H. Y. Chan, Zeljko Zilic:
Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization. ISQED 2005: 390-395 - [c38]Jean-Samuel Chenard, Ahmed Usman Khalid, Milos Prokic, Rong Zhang, K.-L. Lim, Atanu Chattopadhyay, Zeljko Zilic:
Expandable and Robust Laboratory for Microprocessor Systems. MSE 2005: 65-66 - 2004
- [j5]Katarzyna Radecka, Zeljko Zilic:
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. IEEE Trans. Computers 53(5): 628-640 (2004) - [c37]Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka:
FPGA Emulation of Quantum Circuits. ICCD 2004: 310-315 - [c36]Yongquan Fan, Zeljko Zilic:
A novel scheme of implementing high speed AWGN communication channel emulators in FPGAs. ISCAS (2) 2004: 877-880 - [c35]Stuart McCracken, Zeljko Zilic:
Design for Testability of FPGA Blocks. ISQED 2004: 86-91 - [c34]Henry H. Y. Chan, Zeljko Zilic:
Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach. ISQED 2004: 309-314 - [c33]Yongquan Fan, Zeljko Zilic, Man Wah Chiang:
A Versatile High Speed Bit Error Rate Testing Scheme. ISQED 2004: 395-400 - [c32]Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka:
Architectures of Increased Availability Wireless Sensor Network Nodes. ITC 2004: 1232-1241 - [c31]Kahn Li Lim, Zeljko Zilic:
A novel phase detector for PAM-4 clock recovery in high speed serial links. SoCC 2004: 151-152 - 2003
- [c30]Yongquan Fan, Zeljko Zilic:
Testing for bit error rate in FPGA communication interfaces. FPGA 2003: 243 - [c29]Atanu Chattopadhyay, Zeljko Zilic:
A globally asynchronous locally dynamic system for ASICs and SoCs. ACM Great Lakes Symposium on VLSI 2003: 176-181 - [c28]Man Wah Chiang, Zeljko Zilic:
Layered Approach to Designing System Test Interfaces. VTS 2003: 331-338 - 2002
- [j4]Marc Boule, Zeljko Zilic:
An FPGA Move Generator for the Game of Chess. J. Int. Comput. Games Assoc. 25(2): 85-94 (2002) - [j3]Zeljko Zilic, Zvonko G. Vranesic:
A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. IEEE Trans. Computers 51(9): 1100-1105 (2002) - [c27]Marc Boule, Zeljko Zilic:
An FPGA based move generator for the game of chess. CICC 2002: 71-74 - [c26]Stuart McCracken, Zeljko Zilic:
FPGA test time reduction through a novel interconnect testing scheme. FPGA 2002: 136-144 - [c25]Katarzyna Radecka, Zeljko Zilic:
Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. ICCAD 2002: 128-131 - [c24]Weiwen Zhu, Zeljko Zilic, Radu Negulescu:
A single-rail handshake CDMA correlator. ICECS 2002: 505-508 - [c23]Atanu Chattopadhyay, Zeljko Zilic:
High speed asynchronous structures for inter-clock domain communication. ICECS 2002: 517-520 - [c22]Christian Côté, Zeljko Zilic:
Automated SystemC to VHDL translation in hardware/software codesign. ICECS 2002: 717-720 - [c21]Boris Polianskikh, Zeljko Zilic:
Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection. ISMVL 2002: 89-95 - [c20]Zeljko Zilic, Katarzyna Radecka:
The Role of Super-Fast Transforms in Speeding Up Quantum Computations. ISMVL 2002: 129-135 - [c19]Katarzyna Radecka, Zeljko Zilic:
Identifying Redundant Wire Replacements for Synthesis and Verification. ASP-DAC/VLSI Design 2002: 517-523 - 2001
- [c18]Katarzyna Radecka, Zeljko Zilic:
Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. ICCD 2001: 348-353 - [c17]Boris Polianskikh, Zeljko Zilic:
New embedded memory architecture for enhanced yield, performance and power consumption. ICECS 2001: 585-588 - [c16]Henry H. Y. Chan, Zeljko Zilic:
A practical substrate modeling algorithm with active guardband macromodel for mixed-signal substrate coupling verification. ICECS 2001: 1455-1460 - [c15]Katarzyna Radecka, Zeljko Zilic, Karim Khordoc:
Combinational verification by simulations, SAT and BDDs. ICECS 2001: 1627-1630 - [c14]Ian Brynjolfson, Zeljko Zilic:
A new PLL design for clock management applications. ISCAS (4) 2001: 814-817 - [c13]Zeljko Zilic, Katarzyna Radecka:
: Identifying redundant gate replacements in verification by error modeling. ITC 2001: 803-812 - 2000
- [c12]Ian Brynjolfson, Zeljko Zilic:
Dynamic clock management for low power applications in FPGAs. CICC 2000: 139-142 - [c11]Ian Brynjolfson, Zeljko Zilic:
FPGA clock management for low power applications (poster abstract). FPGA 2000: 219 - [c10]R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic:
The NUMAchine Multiprocessor. ICPP 2000: 487-496 - [c9]Katarzyna Radecka, Zeljko Zilic:
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. VTS 2000: 271-280
1990 – 1999
- 1999
- [c8]Zeljko Zilic, Katarzyna Radecka:
On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. ISSAC 1999: 67-74 - [c7]Zeljko Zilic:
Alternatives in Teaching System-Building Skills. MSE 1999: 57-58 - 1998
- [j2]Zeljko Zilic, Zvonko G. Vranesic:
Using Decision Diagrams to Design ULMs for FPGAs. IEEE Trans. Computers 47(9): 970-982 (1998) - [c6]A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic:
Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69 - 1996
- [c5]Stephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic:
Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. DAC 1996: 427-432 - [c4]Zeljko Zilic, Zvonko G. Vranesic:
Using BDDs to Design ULMs for FPGAs. FPGA 1996: 24-30 - [c3]Zeljko Zilic, Zvonko G. Vranesic:
New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. ISMVL 1996: 16-23 - 1995
- [j1]Zeljko Zilic, Zvonko G. Vranesic:
A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. IEEE Trans. Computers 44(8): 1012-1020 (1995) - [c2]Zeljko Zilic, Zvonko G. Vranesic:
Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. ISMVL 1995: 36-43 - 1993
- [c1]Zeljko Zilic, Zvonko G. Vranesic:
Current-Mode CMOS Galois Field Circuits. ISMVL 1993: 245-250
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-23 20:32 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
