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2020 – today
- 2021
[j88]Felix Loh
, Kewal K. Saluja, Parameswaran Ramanathan:
Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method. J. Electron. Test. 37(3): 409-422 (2021)- 2020
- [c164]Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan:
Fault Tolerance through Invariant Checking for the Lanczos Eigensolver. VLSID 2020: 13-18
2010 – 2019
- 2018
- [c163]Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan:
Fault Tolerant Cholesky Factorization on GPUs. FTXS@SC 2018: 11-18 - 2017
- [j87]Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja:
A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. J. Electron. Test. 33(6): 721-739 (2017) - [j86]Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
A Method for Diagnosing Bridging Fault between a Gate Signal Line and a Clock Line. IEICE Trans. Inf. Syst. 100-D(9): 2224-2227 (2017) - [c162]Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja:
Exploiting path delay test generation to develop better TDF tests for small delay defects. ITC 2017: 1-10 - [c161]Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja:
Identifying high variability speed-limiting paths under aging. LATS 2017: 1-6 - 2016
- [j85]Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. IPSJ Trans. Syst. LSI Des. Methodol. 9: 13-20 (2016) - [j84]Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja:
Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks Under Fluid Scheduling Model. ACM Trans. Embed. Comput. Syst. 15(3): 49:1-49:26 (2016) - [c160]Parameswaran Ramanathan, Kewal K. Saluja:
Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay Simulations. ATS 2016: 7-12 - [c159]Kewal K. Saluja:
Digital Testing - Basics to Advanced Research Issues. VLSID 2016: 11 - [c158]Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan:
Fault Tolerance through Invariant Checking for Iterative Solvers. VLSID 2016: 481-486 - 2015
- [c157]Virendra Singh, Adit D. Singh, Kewal K. Saluja:
A Methodology for Identifying High Timing Variability Paths in Complex Designs. ATS 2015: 115-120 - [c156]Kim T. Le, Parmesh Ramanathan, Kewal K. Saluja:
Privacy Assurance in Data-Aggregation for Multiple MAX Transactions. COMPSAC Workshops 2015: 110-115 - [c155]Felix Loh, Parameswaran Ramanathan, Kewal K. Saluja:
Transient Fault Resilient QR Factorization on GPUs. FTXS@HPDC 2015: 63-70 - [c154]Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis of Delay Faults Considering Hazards. ISVLSI 2015: 503-508 - [c153]Rehan Ahmed, Ayoosh Bansal, Bhuvana Kakunoori, Parameswaran Ramanathan, Kewal K. Saluja:
Thermal Extension of the Total Bandwidth Server. VLSID 2015: 47-52 - [c152]Spencer K. Millican, Kewal K. Saluja:
Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints. VLSID 2015: 487-492 - 2014
- [j83]Spencer K. Millican, Kewal K. Saluja:
Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling. J. Electron. Test. 30(5): 569-580 (2014) - [c151]Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja:
Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks. ECRTS 2014: 243-252 - [c150]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults. ISVLSI 2014: 320-325 - [c149]Spencer K. Millican, Kewal K. Saluja:
A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits. VLSID 2014: 20-25 - [c148]Spencer K. Millican, Parameswaran Ramanathan, Kewal K. Saluja:
CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities. VLSID 2014: 92-97 - [c147]Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja:
Temperature Minimization Using Power Redistribution in Embedded Systems. VLSID 2014: 264-269 - 2013
- [j82]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment. IEICE Trans. Inf. Syst. 96-D(6): 1323-1331 (2013) - [c146]Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja:
Diagnosing Resistive Open Faults Using Small Delay Fault Simulation. Asian Test Symposium 2013: 79-84 - [c145]Spencer K. Millican, Kewal K. Saluja:
Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling. Asian Test Symposium 2013: 165-170 - [c144]Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja:
DRMA: dynamically reconfigurable MPSoC architecture. ACM Great Lakes Symposium on VLSI 2013: 239-244 - [c143]Kim T. Le, Parmesh Ramanathan, Kewal K. Saluja:
Privacy Assurances in Multiple Data-Aggregation Transactions. ICISC 2013: 3-19 - [c142]Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja:
On thermal utilization of periodic task sets in uni-processor systems. RTCSA 2013: 267-276 - [c141]Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao:
Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time Systems. VLSI Design 2013: 25-30 - 2012
- [c140]Spencer K. Millican, Kewal K. Saluja:
Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits. Asian Test Symposium 2012: 37-42 - [c139]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis for Bridging Faults on Clock Lines. PRDC 2012: 135-144 - [c138]Warin Sootkaneung, Kewal K. Saluja:
Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate. VLSI Design 2012: 74-79 - 2011
- [j81]Yen-Ting Lin, Kewal K. Saluja, Seapahn Megerian:
Adaptive cost efficient deployment strategy for homogeneous wireless camera sensors. Ad Hoc Networks 9(5): 713-726 (2011) - [j80]Chunhua Yao, Kewal K. Saluja, Parmesh Ramanathan:
Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach. J. Electron. Test. 27(6): 711-721 (2011) - [j79]Chin-Ya Huang, Parameswaran Ramanathan, Kewal K. Saluja:
Routing TCP Flows in Underwater Mesh Networks. IEEE J. Sel. Areas Commun. 29(10): 2022-2032 (2011) - [j78]Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 317-322 (2011) - [c137]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Fault simulation and test generation for clock delay faults. ASP-DAC 2011: 799-805 - [c136]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
On Detecting Transition Faults in the Presence of Clock Delay Faults. Asian Test Symposium 2011: 1-6 - [c135]Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Temperature Dependent Test Scheduling for Multi-core System-on-Chip. Asian Test Symposium 2011: 27-32 - [c134]Tsuyoshi Iwagaki, Kewal K. Saluja:
Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations. DDECS 2011: 175-178 - [c133]Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Enhancement of Clock Delay Faults Testing. ETS 2011: 216 - [c132]Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson:
Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. ICCD 2011: 419-426 - [c131]Krishna Bharath, Chunhua Yao, Nam Sung Kim, Parameswaran Ramanathan, Kewal K. Saluja:
A low cost approach to calibrate on-chip thermal sensors. ISQED 2011: 572-576 - [c130]Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita:
SEU tolerant SRAM cell. ISQED 2011: 597-602 - [c129]Warin Sootkaneung, Kewal K. Saluja:
Soft error reduction through gate input dependent weighted sizing in combinational circuits. ISQED 2011: 603-610 - [c128]Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Thermal-Aware Test Scheduling Using On-chip Temperature Sensors. VLSI Design 2011: 376-381 - 2010
- [j77]Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja:
A Study of Capture-Safe Test Generation Flow for At-Speed Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(7): 1309-1318 (2010) - [j76]Chao Wang, Parameswaran Ramanathan, Kewal K. Saluja:
Modeling latency - lifetime trade-off for target detection in mobile sensor networks. ACM Trans. Sens. Networks 7(1): 8:1-8:24 (2010) - [c127]Hiroshi Yokoyama, Hideo Tamamoto, Kewal K. Saluja:
Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BIST. Asian Test Symposium 2010: 147-152 - [c126]Lin Xie, Azadeh Davoodi, Kewal K. Saluja:
Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. DAC 2010: 274-279 - [c125]Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson:
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. DATE 2010: 1572-1577 - [c124]Warin Sootkaneung, Kewal K. Saluja:
Gate input reconfiguration for combating soft errors in combinational circuits. DSN Workshops 2010: 107-112 - [c123]Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson:
Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. DSN 2010: 121-130 - [c122]Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh:
Modified T-Flip-Flop based scan cell for RAS. ETS 2010: 113-118 - [c121]Sudipta Sarkar, Anubhav Adak, Virendra Singh, Kewal K. Saluja, Masahiro Fujita:
SEU tolerant SRAM for FPGA applications. FPT 2010: 491-494 - [c120]Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson:
Energy-efficient redundant execution for chip multiprocessors. ACM Great Lakes Symposium on VLSI 2010: 143-146 - [c119]Ho-Yong Choi, Kewal K. Saluja:
Detection of inter-port bridging faults in dual-port memories. ISCAS 2010: 657-660 - [c118]A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh:
Test application time minimization for RAS using basis optimization of column decoder. ISCAS 2010: 2614-2617 - [c117]Warin Sootkaneung, Kewal K. Saluja:
On techniques for handling soft errors in digital circuits. ITC 2010: 744-752 - [c116]Yen-Ting Lin, Kewal K. Saluja, Parameswaran Ramanathan:
Connected Barrier Coverage on a Narrow Band: Analysis and Deployment. SECON 2010: 376-384 - [c115]Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh:
On Minimization of Test Application Time for RAS. VLSI Design 2010: 393-398 - [c114]Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja:
Collaborative patrolling for target detection using mobile sensor networks. WCSP 2010: 1-6
2000 – 2009
- 2009
- [j75]Kyuchull Kim, Kewal K. Saluja:
Low-Area Wrapper Cell Design for Hierarchical SoC Testing. J. Electron. Test. 25(6): 347-352 (2009) - [j74]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Addressing Defect Coverage through Generating Test Vectors for Transistor Defects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3128-3135 (2009) - [j73]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu:
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. Inf. Media Technol. 4(4): 727-739 (2009) - [j72]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. IPSJ Trans. Syst. LSI Des. Methodol. 2: 250-262 (2009) - [j71]Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja:
Modeling Detection Latency with Collaborative Mobile Sensing Architecture. IEEE Trans. Computers 58(5): 692-705 (2009) - [c113]Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies. Asian Test Symposium 2009: 281-286 - [c112]Reshma C. Jumani, Niraj Bharatkumar Jain, Virendra Singh, Kewal K. Saluja:
DX-compactor: distributed X-compaction for SoCs. ACM Great Lakes Symposium on VLSI 2009: 505-510 - [c111]Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Power and thermal constrained test scheduling. ITC 2009: 1 - [c110]Chao Wang, Parmesh Ramanathan, Kewal K. Saluja:
Blindly Calibrating Mobile Sensors Using Piecewise Linear Functions. SECON 2009: 1-9 - [c109]Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar:
WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. VLSI Design 2009: 479-484 - [c108]Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar:
False Path Aware Timing Yield Estimation under Variability. VTS 2009: 161-166 - 2008
- [j70]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing. J. Electron. Test. 24(4): 379-391 (2008) - [j69]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Fault Simulation and Test Generation for Transistor Shorts Using Stuck-at Test Tools. IEICE Trans. Inf. Syst. 91-D(3): 690-699 (2008) - [j68]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Maximizing Stuck-Open Fault Coverage Using Stuck-at Test Vectors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3506-3513 (2008) - [j67]Mohammad Gh. Mohammad, Kewal K. Saluja:
Analysis and test procedures for NOR flash memory defects. Microelectron. Reliab. 48(5): 698-709 (2008) - [c107]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Increasing Defect Coverage by Generating Test Vectors for Stuck-Open Faults. ATS 2008: 97-102 - [c106]Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja:
An accurate flip-flop selection technique for reducing logic SER. DSN 2008: 128-136 - [c105]Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja:
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. ETS 2008: 55-60 - [c104]Chao Wang, Parameswaran Ramanathan, Kewal K. Saluja:
Moments Based Blind Calibration in Mobile Sensor Networks. ICC 2008: 896-900 - [c103]Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan:
Implementing high availability memory with a duplication cache. MICRO 2008: 71-82 - [c102]Chao Wang, Parmesh Ramanathan, Kewal K. Saluja:
Calibrating Nonlinear Mobile Sensors. SECON 2008: 533-541 - [c101]Kewal K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang:
NBTI Degradation: A Problem or a Scare? VLSI Design 2008: 137-142 - [c100]Mohammad Gh. Mohammad, Kewal K. Saluja:
Testing Flash Memories for Tunnel Oxide Defects. VLSI Design 2008: 157-162 - 2007
- [j66]Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara:
Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. IEICE Trans. Inf. Syst. 90-D(1): 296-305 (2007) - [j65]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita:
A Novel ATPG Method for Capture Power Reduction during Scan Testing. IEICE Trans. Inf. Syst. 90-D(9): 1398-1405 (2007) - [j64]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 790-800 (2007) - [c99]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator. ATS 2007: 271-274 - [c98]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja:
Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. DAC 2007: 527-532 - [c97]Xiangning Yang, Kewal K. Saluja:
Combating NBTI Degradation via Gate Sizing. ISQED 2007: 47-52 - [c96]Xiangning Yang, Eric F. Weglarz, Kewal K. Saluja:
On NBTI Degradation Process in Digital Logic Circuits. VLSI Design 2007: 723-730 - [c95]Kim T. Le, Dong Hyun Baik, Kewal K. Saluja:
Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. VLSI Design 2007: 769-774 - [c94]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu:
Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. VLSI Design 2007: 781-786 - 2006
- [j63]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch. IEICE Trans. Inf. Syst. 89-D(3): 1165-1172 (2006) - [j62]Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
A New Method for Low-Capture-Power Test Generation for Scan Testing. IEICE Trans. Inf. Syst. 89-D(5): 1679-1686 (2006) - [j61]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita:
A Per-Test Fault Diagnosis Method Based on the X-Fault Model. IEICE Trans. Inf. Syst. 89-D(11): 2756-2765 (2006) - [j60]Tai-Lin Chin, Thomas Clouqueur, Parameswaran Ramanathan, Kewal K. Saluja:
Vulnerability of Surveillance Networks to Faults. Int. J. Distributed Sens. Networks 2(3): 289-311 (2006) - [j59]Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti:
Energy Estimation of the Memory Subsystem in Multiprocessor Systems. J. Low Power Electron. 2(3): 325-332 (2006) - [j58]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1203-1215 (2006) - [c93]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu:
Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. ASP-DAC 2006: 659-664 - [c92]Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu:
Diagnosis of Transistor Shorts in Logic Test Environment. ATS 2006: 354-359 - [c91]Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara:
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. ATS 2006: 409-414 - [c90]Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja:
Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles. GLOBECOM 2006 - [c89]Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja:
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. ICCD 2006: 251-258 - [c88]Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja:
Analytic modeling of detection latency in mobile sensor networks. IPSN 2006: 194-201 - [c87]Dong Hyun Baik, Kewal K. Saluja:
Test Cost Reduction Using Partitioned Grid Random Access Scan. VLSI Design 2006: 169-174 - [c86]Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita:
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. VTS 2006: 58-65 - 2005
- [j57]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
Yield-Driven, False-Path-Aware Clock Skew Scheduling. IEEE Des. Test Comput. 22(3): 214-222 (2005) - [j56]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Delay Fault Testing of Processor Cores in Functional Mode. IEICE Trans. Inf. Syst. 88-D(3): 610-618 (2005) - [j55]Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita:
On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies. IEICE Trans. Inf. Syst. 88-D(4): 703-710 (2005) - [j54]Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita:
Fault Diagnosis of Physical Defects Using Unknown Behavior Model. J. Comput. Sci. Technol. 20(2): 187-194 (2005) - [j53]Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja:
Efficient Test Set Modification for Capture Power Reduction. J. Low Power Electron. 1(3): 319-330 (2005) - [j52]Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu:
A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 252-263 (2005) - [j51]Mohammad Gh. Mohammad, Kewal K. Saluja:
Optimizing program disturb fault tests using defect-based testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 905-915 (2005) - [j50]Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja:
Combinational automatic test pattern generation for acyclic sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 948-956 (2005) - [c85]Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja:
A Class of Linear Space Compactors for Enhanced Diagnostic. Asian Test Symposium 2005: 260-265 - [c84]Dong Hyun Baik, Kewal K. Saluja:
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data Size. Asian Test Symposium 2005: 272-277 - [c83]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Testing Superscalar Processors in Functional Mode. FPL 2005: 747-750 - [c82]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Instruction-based delay fault self-testing of pipelined processor cores. ISCAS (6) 2005: 5686-5689 - [c81]Dong Hyun Baik, Kewal K. Saluja:
Progressive random access scan: a simultaneous solution to test power, test data volume and test time. ITC 2005: 10 - [c80]Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara:
Design and analysis of multiple weight linear compactors of responses containing unknown values. ITC 2005: 10 - [c79]Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
Low-capture-power test generation for scan-based at-speed testing. ITC 2005: 10 - [c78]Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja, Kuang-Ching Wang:
Exposure for collaborative detection using mobile sensor networks. MASS 2005 - [c77]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
False Path and Clock Scheduling Based Yield-Aware Gate Sizing. VLSI Design 2005: 423-426 - [c76]Marong Phadoongsidhi, Kewal K. Saluja:
SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits. VLSI Design 2005: 820-823 - [c75]Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
On Low-Capture-Power Test Generation for Scan Testing. VTS 2005: 265-270 - 2004
- [j49]Thomas Clouqueur, Kewal K. Saluja, Parameswaran Ramanathan:
Fault Tolerance in Collaborative Sensor Networks for Target Detection. IEEE Trans. Computers 53(3): 320-333 (2004) - [c74]Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy:
Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. ETS 2004: 108-113 - [c73]Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
A yield improvement methodology using pre- and post-silicon statistical clock scheduling. ICCAD 2004: 611-618 - [c72]Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
On per-test fault diagnosis using the X-fault model. ICCAD 2004: 633-640 - [c71]Eric F. Weglarz, Kewal K. Saluja, T. M. Mak:
Testing of Hard Faults in Simultaneous Multithreaded Processors. IOLTS 2004: 95-100 - [c70]Matthew L. King, Kewal K. Saluja:
Testing Micropipelined Asynchronous Circuits. ITC 2004: 329-338 - [c69]Marong Phadoongsidhi, Kewal K. Saluja:
Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults. VLSI Design 2004: 437-442 - [c68]Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara:
Random Access Scan: A solution to test power, test data volume and test time. VLSI Design 2004: 883-888 - [c67]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Instruction-Based Delay Fault Self-Testing of Processor Cores. VLSI Design 2004: 933- - 2003
- [j48]Thomas Clouqueur, Veradej Phipatanasuphorn, Parameswaran Ramanathan, Kewal K. Saluja:
Sensor Deployment Strategy for Detection of Targets Traversing a Region. Mob. Networks Appl. 8(4): 453-461 (2003) - [c66]Kewal K. Saluja:
Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits. Asian Test Symposium 2003: 2 - [c65]Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara:
Software-Based Delay Fault Testing of Processor Cores. Asian Test Symposium 2003: 68-71 - [c64]Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita:
Fault Diagnosis for Physical Defects of Unknown Behaviors. Asian Test Symposium 2003: 236-241 - [c63]Mohammad Gh. Mohammad, Kewal K. Saluja:
Stress Test for Disturb Faults in Non-Volatile Memories. Asian Test Symposium 2003: 384-389 - [c62]Marong Phadoongsidhi, Kewal K. Saluja:
Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits. ICCD 2003: 42-47 - [c61]Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja:
Exclusive Test and its Applications to Fault Diagnosis. VLSI Design 2003: 143-148 - [c60]Mohammad Gh. Mohammad, Kewal K. Saluja:
Electrical Model For Program Disturb Faults in Non-Volatile Memories. VLSI Design 2003: 217-222 - 2002
- [j47]Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu:
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3): 362-368 (2002) - [c59]Marong Phadoongsidhi, Kim T. Le, Kewal K. Saluja:
A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits. Asian Test Symposium 2002: 182- - [c58]Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu:
Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. Asian Test Symposium 2002: 242-247 - [c57]Thomas Clouqueur, Veradej Phipatanasuphorn, Parameswaran Ramanathan, Kewal K. Saluja:
Sensor deployment strategy for target detection. WSNA 2002: 42-48 - [c56]Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu:
An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. PRDC 2002: 275-282 - [c55]Fei Li, Lei He, Kewal K. Saluja:
Estimation of Maximum Power-Up Current. ASP-DAC/VLSI Design 2002: 51- - [c54]Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti:
Minimizing Energy Consumption for High-Performance Processing. ASP-DAC/VLSI Design 2002: 199- - [c53]Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja:
Multiple Faults: Modeling, Simulation and Test. ASP-DAC/VLSI Design 2002: 592-597 - 2001
- [j46]Mohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap:
Fault Models and Test Procedures for Flash Memory Disturbances. J. Electron. Test. 17(6): 495-508 (2001) - [c52]Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu:
Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. Asian Test Symposium 2001: 63- - [c51]Keith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu:
On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits. ITC 2001: 568-577 - [c50]Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja:
Combinational test generation for various classes of acyclic sequential circuits. ITC 2001: 1078-1087 - [c49]Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal:
Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. VLSI Design 2001: 143-148 - [c48]Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, Hiroshi Takahashi:
Efficient Signature-Based Fault Diagnosis Using Variable Size Windows. VLSI Design 2001: 391-396 - [c47]Richard M. Chou, Kewal K. Saluja:
Testable Sequential Circuit Design: A Partition and Resynthesis Approach. VTS 2001: 62-67 - [c46]Mohammad Gh. Mohammad, Kewal K. Saluja:
Flash Memory Disturbances: Modeling and Test. VTS 2001: 218-224 - 2000
- [j45]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits. J. Electron. Test. 16(5): 443-451 (2000) - [j44]Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita:
Static test compaction for IDDQ testing of bridging faults in sequential circuits. Syst. Comput. Jpn. 31(11): 41-50 (2000) - [c45]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Fault models and test generation for IDDQ testing: embedded tutorial. ASP-DAC 2000: 509-514 - [c44]Faisal Rashid, Kewal K. Saluja, Parameswaran Ramanathan:
Fault Tolerance through Re-Execution in Multiscalar Architecture. DSN 2000: 482-491 - [c43]Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara:
Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. VLSI Design 2000: 300-305 - [c42]Mohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap:
Testing Flash Memories. VLSI Design 2000: 406-411
1990 – 1999
- 1999
- [c41]Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 141-146 - [c40]Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal:
A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. Great Lakes Symposium on VLSI 1999: 300- - [c39]Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita:
Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. VLSI Design 1999: 72-77 - 1998
- [j43]Kim T. Le, Kewal K. Saluja:
A Heuristic Measure to Maximize Detected Faults per Test. J. Electron. Test. 13(1): 57-60 (1998) - [j42]Yong Chang Kim, Kewal K. Saluja:
Sequential test generators: past, present and future. Integr. 26(1-2): 41-54 (1998) - [j41]Lama Nachman, Kewal K. Saluja, Shambhu J. Upadhyaya, Robert Reuse:
A Novel Approach to Random Pattern Testing of Sequential Circuits. IEEE Trans. Computers 47(1): 129-134 (1998) - [c38]Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita:
Design for Diagnosability of CMOS Circuits. Asian Test Symposium 1998: 144-149 - [c37]Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita:
Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits. Asian Test Symposium 1998: 312-317 - [c36]Seiji Kajihara, Kewal K. Saluja:
On Test Pattern Compaction Using Random Pattern Fault Simulation. VLSI Design 1998: 464-469 - 1997
- [j40]Kwang-Ting Cheng, Kewal K. Saluja, Hans-Joachim Wunderlich:
Guest Editorial. J. Electron. Test. 11(1): 7-8 (1997) - [j39]Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal:
Scheduling tests for VLSI systems under power constraints. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 175-185 (1997) - [c35]Richard M. Chou, Kewal K. Saluja:
Sequential Circuit Testing: From DFT to SFT. VLSI Design 1997: 274-278 - 1996
- [j38]Manoj Franklin, Kewal K. Saluja:
Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1081-1087 (1996) - [j37]Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja:
Incorporating performance and testability constraints during binding in high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1212-1225 (1996) - [j36]Kyuchull Kim, Kewal K. Saluja:
HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits. VLSI Design 4(3): 181-197 (1996) - [c34]Lama Nachman, Kewal K. Saluja, Shambhu J. Upadhyaya, Robert Reuse:
Random Pattern Testing for Sequential Circuits Revisited. FTCS 1996: 44-52 - [c33]Xiaoqing Wen, Kewal K. Saluja:
A new method towards achieving global optimality in technology mapping. ICCAD 1996: 9-12 - [c32]Timothy John Lambert, Kewal K. Saluja:
Methods for Dynamic Test Vector compaction in Sequential Test Generation. VLSI Design 1996: 166-169 - 1995
- [j35]Soo Young Lee, Kewal K. Saluja:
Test application time reduction for sequential circuits with scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1128-1140 (1995) - [c31]Ning Jiang, Richard M. Chou, Kewal K. Saluja:
Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan. FTCS 1995: 41-49 - [c30]Hao Zheng, Kewal K. Saluja, Rajiv Jain:
Test application time reduction for scan based sequential circuits. Great Lakes Symposium on VLSI 1995: 188-191 - [c29]Manoj Franklin, Kewal K. Saluja, Kyuchull Kim:
Fast computation of MISR signatures. VLSI Design 1995: 414-418 - [c28]Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja:
An optimized testable architecture for finite state machines. VTS 1995: 164-169 - 1994
- [j34]Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja:
Incorporating testability considerations in high-level synthesis. J. Electron. Test. 5(1): 43-55 (1994) - [j33]Kewal K. Saluja:
On-chip testing of random access memories. J. Electron. Test. 5(4): 367-376 (1994) - [j32]Manoj Franklin, Kewal K. Saluja:
Hypergraph Coloring and Reconfigured RAM Testing. IEEE Trans. Computers 43(6): 725-736 (1994) - [c27]Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja:
Behavioral Synthesis of Testable Designs. FTCS 1994: 436-445 - [c26]Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal:
Power Constraint Scheduling of Tests. VLSI Design 1994: 271-274 - [c25]Manoj Franklin, Kewal K. Saluja:
An Algorithm to Test Reconfigured RAMs. VLSI Design 1994: 359-364 - [c24]Soo Young Lee, Kewal K. Saluja:
Sequential test generation with reduced test clocks for partial scan designs. VTS 1994: 220-225 - 1993
- [j31]Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja:
A Tutorial on Built-in Self-Test. I. Principles. IEEE Des. Test Comput. 10(1): 73-82 (1993) - [j30]Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja:
A Tutorial on Built-In Self-Test, Part 2: Applications. IEEE Des. Test Comput. 10(2): 69-77 (1993) - [j29]Todd P. Kelsey, Kewal K. Saluja, Soo Young Lee:
An Efficient Algorithm for Sequential Circuit Test Generation. IEEE Trans. Computers 42(11): 1361-1371 (1993) - [j28]Chun-Yeh Liu, Kewal K. Saluja:
An efficient algorithm for bipartite PLA folding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12): 1839-1847 (1993) - [j27]Rajiv Sharma, Kewal K. Saluja:
Theory, Analysis and Implementation of an On-Line BIST Technique. VLSI Design 1(1): 9-22 (1993) - [c23]Soo Young Lee, Kewal K. Saluja:
Efficient Test Vectors for ISCAS Sequential Benchmark Circuits. ISCAS 1993: 1511-1514 - [c22]Kyuchull Kim, Kewal K. Saluja:
CCSTG: an efficient test pattern generator for sequential circuits. VTS 1993: 79-84 - 1992
- [j26]Kewal K. Saluja, Chin-Foo See:
An Efficient Signature Computation Method. IEEE Des. Test Comput. 9(4): 22-26 (1992) - [c21]Ashutosh Mujumdar, Kewal K. Saluja, Rajiv Jain:
Incorporating Testability Considerations in High-Level Systhesis. FTCS 1992: 272-279 - [c20]Soo Young Lee, Kewal K. Saluja:
An algorithm to reduce test application time in full scan designs. ICCAD 1992: 17-20 - [c19]Chin-Foo See, Kewal K. Saluja:
An Efficient Method for Computation of Signatures. VLSI Design 1992: 245-250 - [c18]Kyuchull Kim, Kewal K. Saluja:
On fault deletion problem in concurrent fault simulation for synchronous sequential circuits. VTS 1992: 125-130 - [c17]Parameswaran Ramanathan, Kewal K. Saluja, Michael J. Franklin:
Zero cost testing of check bits in RAMs with on-chip ECC. VTS 1992: 292-297 - 1991
- [j25]Keiho Akiyama, Kewal K. Saluja:
A method of reducing aliasing in a built-in self-test environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 548-553 (1991) - [c16]Manoj Franklin, Kewal K. Saluja:
Pattern Sensitive Fault Testing of RAMs with Bullt-in ECC. FTCS 1991: 385-392 - [c15]Manoj Franklin, Kewal K. Saluja:
An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults. ITC 1991: 675-684 - 1990
- [j24]Manoj Franklin, Kewal K. Saluja:
Built-in Self-testing of Random-Access Memories. Computer 23(10): 45-56 (1990) - [j23]Kewal K. Saluja, Kyuchull Kim:
Improved Test Generation for High-Activity Circuits. IEEE Des. Test Comput. 7(4): 26-31 (1990) - [j22]Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita:
A built-in self-test algorithm for row/column pattern sensitive faults in RAMs. IEEE J. Solid State Circuits 25(2): 514-524 (1990) - [j21]Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan:
Design and Analysis of a Gracefully Degrading Interleaved Memory System. IEEE Trans. Computers 39(1): 63-71 (1990)
1980 – 1989
- 1989
- [c14]Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita:
Row/column pattern sensitive fault detection in RAMs via built-in self-test. FTCS 1989: 36-43 - [c13]Gurindar S. Sohi, Manoj Franklin, Kewal K. Saluja:
A study of time-redundant fault tolerance techniques for high-performance pipelined computers. FTCS 1989: 436-443 - [c12]Todd P. Kelsey, Kewal K. Saluja:
Fast test generation for sequential circuits. ICCAD 1989: 345-347 - [c11]Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita:
Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. ITC 1989: 327-336 - 1988
- [j20]Shambhu J. Upadhyaya, Kewal K. Saluja:
An experimental study to determine task size for rollback recovery systems. IEEE Trans. Computers 37(6): 872-877 (1988) - [j19]Gary L. Craig, Charles R. Kime, Kewal K. Saluja:
Test Scheduling and Control for VLSI Built-In Self-Test. IEEE Trans. Computers 37(9): 1099-1109 (1988) - [j18]Sudhakar M. Reddy, Kewal K. Saluja, Mark G. Karpovsky:
A Data Compression Technique for Built-In Self-Test. IEEE Trans. Computers 37(9): 1151-1156 (1988) - [j17]Shambhu J. Upadhyaya, Kewal K. Saluja:
A new approach to the design of built-in self-testing PLAs for high fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 60-67 (1988) - [j16]Kewal K. Saluja, Rajiv Sharma, Charles R. Kime:
A concurrent testing technique for digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12): 1250-1260 (1988) - [c10]Rajiv Sharma, Kewal K. Saluja:
An implementation and analysis of a concurrent built-in self-test technique. FTCS 1988: 164-169 - 1987
- [j15]Kewal K. Saluja, Siew H. Sng, Kozo Kinoshita:
Built-In Self-Testing RAM: A Practical Alternative. IEEE Des. Test 4(1): 42-51 (1987) - [c9]Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya:
BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays. DAC 1987: 385-391 - [c8]Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan:
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. ISCA 1987: 224-231 - 1986
- [j14]Kewal K. Saluja, Ramaswami Dandapani:
An Alternative to Scan Design Methods for Sequential Machines. IEEE Trans. Computers 35(4): 384-388 (1986) - [j13]Kewal K. Saluja, Ramaswami Dandapani:
Testable Design of Single-Output Sequential Machines Using Checking Experiments. IEEE Trans. Computers 35(7): 658-662 (1986) - [j12]Kozo Kinoshita, Kewal K. Saluja:
Built-In Testing of Memory Using an On-Chip Compact Testing Scheme. IEEE Trans. Computers 35(10): 862-870 (1986) - [j11]Shambhu J. Upadhyaya, Kewal K. Saluja:
A Wachtdog Processor Based General Rollback Technique with Multiple Retries. IEEE Trans. Software Eng. 12(1): 87-95 (1986) - [c7]Kim T. Le, Kewal K. Saluja:
A Novel Approach for Testing Memories Using a Built-In Self Testing Technique. ITC 1986: 830-839 - 1985
- [j10]C. Boswell, Kewal K. Saluja, Kozo Kinoshita:
Design of Programmable Logic Arrays for Parallel Testing. Comput. Syst. Sci. Eng. 1(1): 5-16 (1985) - [j9]Kewal K. Saluja, Kozo Kinoshita:
Test Pattern Generation for API Faults in RAM. IEEE Trans. Computers 34(3): 284-287 (1985) - [c6]Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita:
A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. ITC 1985: 574-582 - 1984
- [j8]Kewal K. Saluja, Kim Thang Le:
Testable design of large random access memories. Integr. 2(4): 309-330 (1984) - [c5]Kozo Kinoshita, Kewal K. Saluja:
Built-in Testing of Memory Using On-chip Compact Testing Scheme. ITC 1984: 271-281 - 1983
- [j7]Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara:
An Easily Testable Design of Programmable Logic Arrays for Multiple Faults. IEEE Trans. Computers 32(11): 1038-1046 (1983) - [c4]Kewal K. Saluja, Mark G. Karpovsky:
Testing Computer Hardware through Data Compression in Space and Time. ITC 1983: 83-88 - [c3]Kewal K. Saluja, Li Shen, Stephen Y. H. Su:
A Simplified Algorithm for Testing Microprocessors. ITC 1983: 668-675 - 1982
- [c2]Kewal K. Saluja:
An enhancement of lssd to reduce test pattern generation effort and increase fault coverage. DAC 1982: 489-494 - 1980
- [j6]Kewal K. Saluja, Brian D. O. Anderson:
Fault diagnosis in loop-connected systems. Inf. Sci. 21(1): 75-92 (1980) - [j5]Kewal K. Saluja:
Synchronous Sequential Machines: A Modular and Testable Design. IEEE Trans. Computers 29(11): 1020-1025 (1980)
1970 – 1979
- 1979
- [j4]Kewal K. Saluja, E. H. Ong:
Minimization of Reed-Muller Canonic Expansion. IEEE Trans. Computers 28(7): 535-537 (1979) - 1975
- [j3]Kewal K. Saluja, Sudhakar M. Reddy:
Fault Detecting Test Sets for Reed-Muller Canonic Networks. IEEE Trans. Computers 24(10): 995-998 (1975) - 1974
- [j2]Kewal K. Saluja, Sudhakar M. Reddy:
On Minimally Testable Logic Networks. IEEE Trans. Computers 23(5): 552-554 (1974) - [j1]Kewal K. Saluja, Sudhakar M. Reddy:
Easily Testable Two-Dimensional Cellular Logic Arrays. IEEE Trans. Computers 23(11): 1204-1207 (1974) - 1972
- [c1]Kewal K. Saluja, Sudhakar M. Reddy:
Multiple Faults in Reed-Muller Canonic Networks. SWAT 1972: 185-191
Coauthor Index
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