TAO: two-level atomicity for dynamic binary optimizations. - Borin, Edson; Wu, Youfeng; Wang, Cheng; Liu, Wei; Breternitz, Maurício, Jr.; Hu, Shiliang; Natanzon, Esfir; Rotem, Shai; Rosner, Roni (2010)

Relative timing [asynchronous design]. - Stevens, Ken S.; Ginosar, Ran; Rotem, Shai (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Coordinated transformations for high-level synthesis of high performance microprocessor blocks. - Gupta, Sumit; Savoiu, Nick; Dutt, Nikil D.; Gupta, Rajesh K.; Nicolau, Alexandru; Kam, Timothy; Kishinevsky, Michael; Rotem, Shai (2002)

An asynchronous instruction length decoder. - Stevens, Kenneth S.; Rotem, Shai; Ginosar, Ran; Beerel, Peter A.; Myers, Chris J.; Yun, Kenneth Y.; Kol, Rakefet; Dike, Charles; Roncken, Marly (IEEE J. Solid State Circuits, 2001)

CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. - Roncken, Marly; Stevens, Ken S.; Pendurkar, Rajesh; Rotem, Shai; Chaudhuri, Parimal Pal (2000)

RAPPID: An Asynchronous Instruction Length Decoder. - Rotem, Shai; Stevens, Ken S.; Dike, Charles; Roncken, Marly; Agapiev, Boris; Ginosar, Ran; Kol, Rakefet; Beerel, Peter A.; Myers, Chris J.; Yun, Kenneth Y. (1999)

Relative Timing. - Stevens, Ken S.; Rotem, Shai; Ginosar, Ran (1999)

CAD Directions for High Performance Asynchronous Circuits. - Stevens, Ken S.; Rotem, Shai; Burns, Steven M.; Cortadella, Jordi; Ginosar, Ran; Kishinevsky, Michael; Roncken, Marly (1999)

Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. - Chou, Wei-Chun; Beerel, Peter A.; Ginosar, Ran; Kol, Rakefet; Myers, Chris J.; Rotem, Shai; Stevens, Ken S.; Yun, Kenneth Y. (1998)