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ORCIDJustin E. Harlow III
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2000 – 2009
- 2007
[j4]R. Iris Bahar
, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram:
Architectures for Silicon Nanoelectronics and Beyond. Computer 40(1): 25-33 (2007)- 2006
- [c7]Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III:
A novel approach for variation aware power minimization during gate sizing. ISLPED 2006: 174-179 - 2003
- [c6]Justin E. Harlow III:
Toward Design Technology in 2020: Trends, Issues, and Challenges. ISVLSI 2003: 3-4 - 2001
- [j3]Justin E. Harlow III, Franc Brglez:
Design of experiments and evaluation of BDD ordering heuristics. Int. J. Softw. Tools Technol. Transf. 3(2): 193-206 (2001) - 2000
- [j2]Scott Davidson, Justin E. Harlow III:
Guest Editors' Introduction: Benchmarking for Design and Test. IEEE Des. Test Comput. 17(3): 12-14 (2000) - [j1]Justin E. Harlow III:
Overview of Popular Benchmark Sets. IEEE Des. Test Comput. 17(3): 15-17 (2000)
1990 – 1999
- 1999
- [c5]Justin E. Harlow III, Franc Brglez:
Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. ISCAS (6) 1999: 452-455 - 1998
- [c4]Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III:
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. DATE 1998: 656-663 - [c3]Justin E. Harlow III, Franc Brglez:
Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations. FMCAD 1998: 64-81 - [c2]Justin E. Harlow III, Franc Brglez:
Design of experiments in BDD variable ordering: lessons learned. ICCAD 1998: 646-652
1970 – 1979
- 1977
- [c1]Justin E. Harlow III:
The open shop interactive mask design operation at harris semiconductor. DAC 1977: 331-335
Coauthor Index
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