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ORCIDEduardo I. Boemo
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2020 – today
- 2020
[j8]Sergio Ruben Geninatti
, Eduardo I. Boemo:
Real-Time Reconfigurable Processor to Detect Similarities in Compressed Video Using Generalized Hough Transformation. IEEE Trans. Circuits Syst. Video Technol. 30(9): 2932-2946 (2020)
2010 – 2019
- 2019
- [j7]Juan P. Oliver, Federico Favaro, Eduardo I. Boemo:
A Framework to Compare Estimated and Measured Power Consumption on FPGAs. J. Low Power Electron. 15(4): 329-337 (2019) - 2017
- [j6]Juan P. Oliver, Francisco Veirano, Diego A. Bouvier, Eduardo I. Boemo:
A Low Cost System for Self Measurements of Power Consumption in Field Programmable Gate Arrays. J. Low Power Electron. 13(1): 1-9 (2017) - 2013
- [j5]Javier Hormigo, Gabriel Caffarena, Juan P. Oliver, Eduardo I. Boemo:
Self-Reconfigurable Constant Multiplier for FPGA. ACM Trans. Reconfigurable Technol. Syst. 6(3): 14:1-14:17 (2013) - [c21]Eduardo I. Boemo, Juan P. Oliver, Gabriel Caffarena:
Tracking the pipelining-power rule along the FPGA technical literature. FPGAworld 2013: 9:1-9:5
2000 – 2009
- 2008
- [c20]David M. Cambre, Eduardo I. Boemo, Elias Todorovich:
Arithmetic Operations and Their Energy Consumption in the Nios II Embedded Processor. ReConFig 2008: 151-156 - 2007
- [j4]Philip Heng Wai Leong, Andreas Koch, Eduardo I. Boemo:
Editorial - Field-programmable logic and applications. IET Comput. Digit. Tech. 1(4): 265-266 (2007) - 2006
- [c19]J. Gonzalez-Gomez, Iván González, Francisco J. Gomez-Arribas, Eduardo I. Boemo:
Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors. ARC 2006: 24-29 - [c18]Elias Todorovich, Eduardo I. Boemo:
A-B Nodes Classification for Power Estimation. FPL 2006: 1-6 - 2005
- [c17]J. Gonzalez-Gomez, Eduardo I. Boemo:
Motion of Minimal Configurations of a Modular Robot: Sinusoidal, Lateral Rolling and Lateral Shift. CLAWAR 2005: 667-674 - [c16]Elias Todorovich, Fabian Angarita, Javier Valls, Eduardo I. Boemo:
Statistical Power Estimation for FPGA. FPL 2005: 515-518 - [c15]Susana Ortega-Cisneros, Juan José Raygoza-Panduro, Juan Suardíaz Muro, Eduardo I. Boemo:
Rapid prototyping of a self-timed ALU with FPGAs. ReConFig 2005 - [c14]Juan José Raygoza-Panduro, Susana Ortega-Cisneros, Eduardo I. Boemo:
FPGA implementation of a synchronous and self-timed neuroprocessor. ReConFig 2005 - 2004
- [c13]Sergio López-Buedo, Eduardo I. Boemo:
Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report. FPGA 2004: 79-86 - [c12]Elias Todorovich, Eduardo I. Boemo, Francisco Cardells-Tormo, Javier Valls:
Power analysis and estimation tool integrated with XPOWER. FPGA 2004: 259 - [c11]Gustavo Sutter, Jean-Pierre Deschamps, Gery Bioul, Eduardo I. Boemo:
Power Aware Dividers in FPGA. PATMOS 2004: 574-584 - [i1]C. M. Gonzalez, Hilda A. Larrondo, C. A. Gayoso, Leonardo J. Arnone, Eduardo I. Boemo:
Digital Signal Transmission with Chaotic Encryption: Design and Evaluation of a FPGA Realization. CoRR cs.CR/0402056 (2004) - 2003
- [j3]Javier Valls, Eduardo I. Boemo:
Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers. IEEE Trans. Circuits Syst. II Express Briefs 50(6): 317-322 (2003) - 2002
- [c10]Sergio López-Buedo, Paula Riviere, Pablo Pernas, Eduardo I. Boemo:
Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology. FPL 2002: 162-170 - [c9]Elias Todorovich, M. Gilabert, Gustavo Sutter, Sergio López-Buedo, Eduardo I. Boemo:
A Tool for Activity Estimation in FPGAs. FPL 2002: 340-349 - [c8]Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo:
FSM Decomposition for Low Power in FPGA. FPL 2002: 350-359 - [c7]Gustavo Sutter, Elias Todorovich, Sergio López-Buedo, Eduardo I. Boemo:
Low-Power FSMs in FPGA: Encoding Alternatives. PATMOS 2002: 363-370 - 2000
- [j2]Sergio López-Buedo, Javier Garrido Salas, Eduardo I. Boemo:
Thermal Testing on Reconfigurable Computers. IEEE Des. Test Comput. 17(1): 84-91 (2000)
1990 – 1999
- 1999
- [c6]Marcos Martínez-Peiró, Javier Valls, T. Sansaloni, A. Perez-Pascual, Eduardo I. Boemo:
A comparison between lattice, cascade and direct form FIR filter structures by using a FPGA bit-serial distributed arithmetic implementation. ICECS 1999: 241-244 - [c5]Javier Valls, Trini Sansaloni, Marcos Martínez-Peiró, Eduardo I. Boemo:
Fast FPGA-based pipelined digit-serial/parallel multipliers. ISCAS (1) 1999: 482-485 - 1998
- [j1]Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses:
Some experiments about wave pipelining on FPGA's. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 232-237 (1998) - [c4]Javier Valls, Marcos M. Peiró, Trinidad Sansaloni, Eduardo I. Boemo:
Design and FPGA implementation of digit-serial FIR filters. ICECS 1998: 191-194 - 1997
- [c3]Eduardo I. Boemo, Sergio López-Buedo:
Thermal monitoring on FPGAs using ring-oscillators. FPL 1997: 69-78 - 1996
- [c2]Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses:
The Wave Pipeline Effect on LUT-Based FPGA Architectures. FPGA 1996: 45-50 - 1995
- [c1]Eduardo I. Boemo, Guillermo González de Rivera, Sergio López-Buedo, Juan M. Meneses:
Some Notes on Power Management on FPGA-Based Systems. FPL 1995: 149-157
Coauthor Index
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