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ORCIDChris Lavin
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- affiliation: Xilinx Research Labs, Longmont, CO, USA
- affiliation: Xilinx, San Jose, CA, USA
- affiliation: Brigham Young University, Provo, UT, USA
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2020 – today
- 2024
[c14]Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne:
DynaRapid: Fast-Tracking from C to Routed Circuits. FPL 2024: 24-32- 2023
- [j4]Licheng Guo
, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong:
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 16(4): 59:1-59:30 (2023) - [c13]Dana How, Tim Ansell, Vaughn Betz, Chris Lavin, Ted Speers, Pierre-Emmanuel Gaillardon:
Open-source and FPGAs: Hardware, Software, Both or None? FPGA 2023: 149 - [c12]Chris Lavin, Eddie Hung:
Invited Paper: RapidWright: Unleashing the Full Power of FPGA Technology with Domain-Specific Tooling. ICCAD 2023: 1-7 - 2022
- [j3]Yun Zhou, Pongstorn Maidee, Chris Lavin, Alireza Kaviani, Dirk Stroobandt:
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(1): 8:1-8:27 (2022) - [c11]Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong:
RapidStream: Parallel Physical Implementation of FPGA HLS Designs. FPGA 2022: 1-12 - 2021
- [c10]James Thomas, Chris Lavin, Alireza Kaviani:
Software-like Compilation for Data Center FPGA Accelerators. HEART 2021: 3:1-3:6 - [d1]Yun Zhou, Pongstorn Maidee, Chris Lavin, Alireza Kaviani, Dirk Stroobandt:
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs. Zenodo, 2021
2010 – 2019
- 2019
- [c9]Chris Lavin, Alireza Kaviani:
Build Your Own Domain-specific Solutions with RapidWright: Invited Tutorial. FPGA 2019: 14-22 - [c8]Pongstorn Maidee, Chris Neely, Alireza Kaviani, Chris Lavin:
An Open-Source Lightweight Timing Model for RapidWright. FPT 2019: 171-178 - 2018
- [c7]Chris Lavin, Alireza Kaviani:
RapidWright: Enabling Custom Crafted Implementations for FPGAs. FCCM 2018: 133-140 - 2017
- [j2]Michael Rice, Joseph M. Palmer, Christopher Lavin, Tom Nelson:
Space-Time Coding for Aeronautical Telemetry: Part I - Estimators. IEEE Trans. Aerosp. Electron. Syst. 53(4): 1709-1731 (2017) - [j1]Michael Rice, Tom Nelson, Joseph M. Palmer, Christopher Lavin, Kip Temple:
Space-Time Coding for Aeronautical Telemetry: Part II - Decoder and System Performance. IEEE Trans. Aerosp. Electron. Syst. 53(4): 1732-1754 (2017) - 2013
- [c6]Christopher Lavin, Brent E. Nelson, Brad L. Hutchings:
Impact of hard macro size on FPGA clock rate and place/route time. FPL 2013: 1-6 - [c5]Christopher Lavin, Brent E. Nelson, Brad L. Hutchings:
Improving clock-rate of hard-macro designs. FPT 2013: 246-253 - 2011
- [c4]Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings:
HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping. FCCM 2011: 117-124 - [c3]Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings:
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs. FPL 2011: 349-355 - 2010
- [c2]Christopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin:
Using Hard Macros to Reduce FPGA Compilation Time. FPL 2010: 438-441 - [c1]Christopher Lavin, Marc Padilla, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings:
Rapid prototyping tools for FPGA designs: RapidSmith. FPT 2010: 353-356
Coauthor Index
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