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ORCIDStanislaw J. Piestrak
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2020 – today
- 2023
[j25]Piotr Patronik
, Stanislaw J. Piestrak:
Design of reverse converters for the general RNS 3-moduli set {2k, 2n - 1, 2n + 1}. EURASIP J. Adv. Signal Process. 2023(1): 92 (2023)
2010 – 2019
- 2018
- [j24]Piotr Patronik, Stanislaw J. Piestrak:
Correction to: Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2k, 2n-1, 2n+1, 2n+1-1, 2n-1-1} (n Even). Circuits Syst. Signal Process. 37(11): 5197 (2018) - [j23]Piotr Patronik, Stanislaw J. Piestrak:
Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels. J. Signal Process. Syst. 90(3): 323-339 (2018) - 2017
- [j22]Piotr Patronik, Stanislaw J. Piestrak:
Design of Reverse Converters for a New Flexible RNS Five-Moduli Set {2k, 2n-1, 2n+1, 2n+1-1, 2n-1-1} (n Even). Circuits Syst. Signal Process. 36(11): 4593-4614 (2017) - [j21]Piotr Patronik, Stanislaw J. Piestrak:
Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1031-1039 (2017) - [c33]Piotr Patronik, Stanislaw J. Piestrak:
Design of residue generators with CLA/compressor trees and multi-bit EAC. LASCAS 2017: 1-4 - 2016
- [c32]Piotr Patronik, Stanislaw J. Piestrak:
Design of a low-power RNS-enhanced arithmetic unit. LASCAS 2016: 151-154 - 2015
- [j20]Stanislaw J. Piestrak:
A note on RNS architectures for the implementation of the diagonal function. Inf. Process. Lett. 115(4): 453-457 (2015) - [c31]B. Chagun Basha, Sébastien Pillement, Stanislaw J. Piestrak:
Fault-aware configurable logic block for reliable reconfigurable FPGAs. ISCAS 2015: 2732-2735 - [c30]Stanislaw J. Piestrak, Piotr Patronik:
Fault-tolerant implementation of direct FIR filters protected using residue codes. NORCAS 2015: 1-4 - 2014
- [j19]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Private reliability environments for efficient fault-tolerance in CGRAs. Des. Autom. Embed. Syst. 18(3-4): 295-327 (2014) - [j18]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of the coarse-grained reconfigurable architecture DART with on-line error detection. Microprocess. Microsystems 38(2): 124-136 (2014) - [j17]Piotr Patronik, Stanislaw J. Piestrak:
Design of Reverse Converters for General RNS Moduli Sets {2k, 2n-1, 2n+1, 2n+1-1} and {2k, 2n-1, 2n+1, 2n-1-1} (n even). IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(6): 1687-1700 (2014) - [j16]Piotr Patronik, Stanislaw J. Piestrak:
Design of Reverse Converters for the New RNS Moduli Set {2n+1, 2n-1, 2n, 2n-1+1} (n odd). IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3436-3449 (2014) - [c29]B. Chagun Basha, Stanislaw J. Piestrak, Sébastien Pillement:
Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs. ARC 2014: 254-261 - [c28]Stanislaw J. Piestrak, Piotr Patronik:
Design of Fault-Secure Transposed FIR Filters Protected Using Residue Codes. DSD 2014: 575-582 - 2013
- [j15]Hung-Manh Pham, Sébastien Pillement, Stanislaw J. Piestrak:
Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor. IEEE Trans. Computers 62(6): 1179-1192 (2013) - [c27]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen:
Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. DSD 2013: 525-534 - [c26]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen:
Implementation and evaluation of configuration scrubbing on CGRAs: A case study. ISSoC 2013: 1-8 - 2012
- [c25]Piotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava:
Design of an RNS reverse converter for a new five-moduli special set. ACM Great Lakes Symposium on VLSI 2012: 67-70 - 2011
- [c24]Muhammad Moazam Azeem, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Error recovery technique for coarse-grained reconfigurable architectures. DDECS 2011: 441-446 - [c23]Stanislaw J. Piestrak:
Design of multi-residue generators using shared logic. ISCAS 2011: 1435-1438 - [c22]Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava:
Fast and energy-efficient constant-coefficient FIR filters using residue number system. ISLPED 2011: 385-390 - 2010
- [j14]Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys:
Comments on "A Low-Power Dependable Berger Code for Fully Asymmetric Communication". IEEE Commun. Lett. 14(8): 761-763 (2010) - [j13]Stanislaw J. Piestrak, Sébastien Pillement, Olivier Sentieys:
Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication. IEEE Trans. Circuits Syst. II Express Briefs 57-II(10): 777-781 (2010) - [c21]Stanislaw J. Piestrak:
On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels. DSD 2010: 133-140 - [c20]Stanislaw J. Piestrak:
Design of cost-efficient multipliers modulo 2a-1. ISCAS 2010: 4093-4096 - [c19]Syed M. A. H. Jafri, Stanislaw J. Piestrak, Olivier Sentieys, Sébastien Pillement:
Design of a fault-tolerant coarse-grained. ISQED 2010: 845-852
2000 – 2009
- 2009
- [j12]Houssein Jaber, Fabrice Monteiro, Stanislaw J. Piestrak, Abbas Dandache:
Design of parallel fault-secure encoders for systematic cyclic block transmission codes. Microelectron. J. 40(12): 1686-1697 (2009) - [c18]Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak:
Exploiting residue number system for power-efficient digital signal processing in embedded processors. CASES 2009: 19-28 - 2007
- [c17]Fabrice Monteiro, Stanislaw J. Piestrak, Houssein Jaber, Abbas Dandache:
Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes. IOLTS 2007: 199-200 - 2006
- [c16]Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache, Stéphane Rossignol, Pascal Moitrel:
Characterizing Laser-Induced Pulses in ICs: Methodology and Results. IOLTS 2006: 11-16 - 2005
- [c15]Damien Leroy, Stanislaw J. Piestrak, Fabrice Monteiro, Abbas Dandache:
Modeling of Transients Caused by a Laser Attack on Smart Cards. IOLTS 2005: 193-194 - 2003
- [j11]Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro:
Designing fault-secure parallel encoders for systematic linear error correcting codes. IEEE Trans. Reliab. 52(4): 492-500 (2003) - 2002
- [j10]Stanislaw J. Piestrak:
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes. IEEE Trans. Computers 51(2): 229-234 (2002) - [j9]Stanislaw J. Piestrak:
Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'. IEEE Trans. Computers 51(6): 735-736 (2002) - [c14]Stanislaw J. Piestrak:
Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage. DFT 2002: 354-364 - 2001
- [c13]Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro:
Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes. DFT 2001: 314- - [c12]Stanislaw J. Piestrak, Dimitris Bakalis, Xrysovalantis Kavousianos:
On the Design of Self-Testing Checkers for Modified Berger Codes. IOLTW 2001: 153-157
1990 – 1999
- 1999
- [c11]Jerzy W. Greblicki, Stanislaw J. Piestrak:
Design of Totally Self-Checking Code-Disjoint Synchronous Sequential Circuits. EDCC 1999: 251-266 - 1998
- [j8]Stanislaw J. Piestrak:
Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters. J. Electron. Test. 12(1-2): 63-68 (1998) - [c10]Stanislaw J. Piestrak:
Membership Test Logic for Delay-Insensitive Codes. ASYNC 1998: 194- - [c9]Stanislaw J. Piestrak, Fabrice Pedron, Olivier Sentieys:
VLSI implementation and complexity comparison of residue generators modulo 3. EUSIPCO 1998: 1-4 - 1997
- [c8]Stanislaw J. Piestrak:
Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes. DFT 1997: 119-127 - 1996
- [j7]Stanislaw J. Piestrak:
Self-Checking Design in Eastern Europe. IEEE Des. Test Comput. 13(1): 16-25 (1996) - [j6]Stanislaw J. Piestrak:
Design of Self-Testing Checkers for Borden Codes. IEEE Trans. Computers 45(4): 461-469 (1996) - [j5]Stanislaw J. Piestrak:
Design of minimal-level PLA self-testing checkers for m-out-of-n codes. IEEE Trans. Very Large Scale Integr. Syst. 4(2): 264-272 (1996) - 1995
- [b1]Stanislaw J. Piestrak:
Design of self-testing checkers for unidirectional error detecting codes. Technical University of Wroclaw, Poland, Scientific papers of the Institute of Technical Cybernetics of the Technical University of Wroclaw 24, 1995, pp. 1-111 - [c7]Stanislaw J. Piestrak, Takashi Nanya:
Towards Totally Self-Checking Delay-Insensitive Systems. FTCS 1995: 228-237 - 1994
- [j4]Stanislaw J. Piestrak:
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders. IEEE Trans. Computers 43(1): 68-77 (1994) - [c6]Stanislaw J. Piestrak:
Design of TSC Code-Disjoint Inverter-Free PLA's for Separable Unordered Codes. ICCD 1994: 128-131 - [c5]Stanislaw J. Piestrak:
Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder Theorem. ICCD 1994: 508-511 - 1993
- [j3]Stanislaw J. Piestrak:
The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks. IEEE Trans. Computers 42(6): 700-712 (1993) - 1991
- [c4]Stanislaw J. Piestrak:
Design of residue generators and multioperand modular adders using carry-save adders. IEEE Symposium on Computer Arithmetic 1991: 100-107 - [c3]Stanislaw J. Piestrak:
Design of a Self-Testing Checker for Borden Code. ICCD 1991: 582-585 - [c2]Stanislaw J. Piestrak:
Efficient Encoding? Decoding Circuitry for Systematic Unidirectional Error-Detecting Codes. Fault-Tolerant Computing Systems 1991: 181-192 - 1990
- [j2]Stanislaw J. Piestrak:
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes. IEEE Trans. Computers 39(3): 360-374 (1990) - [c1]Stanislaw J. Piestrak:
The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes. FTCS 1990: 457-464
1980 – 1989
- 1987
- [j1]Stanislaw J. Piestrak:
Design of Fast Self-Testing Checkers for a Class of Berger Codes. IEEE Trans. Computers 36(5): 629-634 (1987)
Coauthor Index
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