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ORCIDMorteza Saheb Zamani
2020 – today
- 2023
[j39]Ali Suvizi
, Azim Farghadan, Morteza Saheb Zamani:
A parallel computing architecture based on cellular automata for hydraulic analysis of water distribution networks. J. Parallel Distributed Comput. 178: 11-28 (2023)- [j38]Eesa Nikahd, Morteza Saheb Zamani, Mehdi Sedighi:
Low-overhead code concatenation approaches for universal quantum computation. Quantum Inf. Process. 22(1): 73 (2023) - [j37]Vahid Amini, Mahmoud Momtazpour, Morteza Saheb Zamani:
An energy-efficient and accuracy-aware edge computing framework for heart arrhythmia detection: A joint model selection and task offloading approach. J. Supercomput. 79(8): 8178-8204 (2023) - 2022
- [j36]Mohammad Hadi Mottaghi, Mehdi Sedighi, Morteza Saheb Zamani:
FIFA: A Fully Invertible FPGA Architecture to Reduce BTI-Induced Aging Effects. IEEE Trans. Computers 71(9): 2277-2286 (2022) - [j35]Reza Fani, Morteza Saheb Zamani:
Runtime hardware Trojan detection by reconfigurable monitoring circuits. J. Supercomput. 78(10): 12726-12752 (2022) - 2021
- [i10]Sahar Darafsh, Saeed Shiry Ghidary, Morteza Saheb Zamani:
Real-Time Activity Recognition and Intention Recognition Using a Vision-based Embedded System. CoRR abs/2107.12744 (2021) - 2020
- [j34]Mona Arabzadeh, Mehdi Sedighi, Morteza Saheb Zamani, Sayed-Amir Marashi:
A system architecture for parallel analysis of flux-balanced metabolic pathways. Comput. Biol. Chem. 88: 107309 (2020) - [j33]Ghobad Zarrinchian, Morteza Saheb Zamani:
Combinational Counters: A Low Overhead Approach to Address DPA Attacks. J. Circuits Syst. Comput. 29(6): 2050097:1-2050097:19 (2020) - [j32]Mohammad Hadi Mottaghi, Mehdi Sedighi, Morteza Saheb Zamani:
Aging Mitigation in FPGAs Considering Delay, Power, and Temperature. IEEE Trans. Reliab. 69(2): 833-844 (2020)
2010 – 2019
- 2018
- [j31]Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Sayed-Amir Marashi:
A graph-based approach to analyze flux-balanced pathways in metabolic networks. Biosyst. 165: 40-51 (2018) - 2017
- [j30]Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani, Kourosh Marjoei:
Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics. ACM J. Emerg. Technol. Comput. Syst. 13(4): 55:1-55:27 (2017) - [j29]Ghobad Zarrinchian, Morteza Saheb Zamani:
Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan Detection. IEEE Trans. Computers 66(1): 100-113 (2017) - [i9]Maryam Eslamy, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi:
Geometry-Based Optimization of One-Way Quantum Computation Measurement Patterns. CoRR abs/1704.07378 (2017) - 2016
- [j28]Mehrshad Khosraviani, Morteza Saheb Zamani, Gholamreza Bidkhori:
FogLight: an efficient matrix-based approach to construct metabolic pathways by search space reduction. Bioinform. 32(3): 398-408 (2016) - [j27]Mona Arabzadeh, Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani:
Quantum-Logic Synthesis of Hermitian Gates. ACM J. Emerg. Technol. Comput. Syst. 12(4): 40:1-40:15 (2016) - [i8]Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi:
One-Way Quantum Computer Simulation. CoRR abs/1604.05659 (2016) - 2015
- [j26]Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Monireh Houshmand:
GA-based approach to find the stabilizers of a given sub-space. Genet. Program. Evolvable Mach. 16(1): 57-71 (2015) - [j25]Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani:
A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust. J. Circuits Syst. Comput. 24(8): 1550115:1-1550115:30 (2015) - [j24]Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani:
Improving hardware Trojan detection by retiming. Microprocess. Microsystems 39(3): 145-156 (2015) - [j23]Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi:
One-way quantum computer simulation. Microprocess. Microsystems 39(3): 210-222 (2015) - 2014
- [j22]Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh:
Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates. ACM J. Emerg. Technol. Comput. Syst. 11(3): 28:1-28:10 (2014) - [j21]Arash Nejat, Seyed Mohammad Hossein Shekarian, Morteza Saheb Zamani:
A study on the efficiency of hardware Trojan detection based on path-delay fingerprinting. Microprocess. Microsystems 38(3): 246-252 (2014) - [j20]Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi:
Quantum circuit physical design methodology with emphasis on physical synthesis. Quantum Inf. Process. 13(2): 445-465 (2014) - [j19]Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mohammad Hossein Samavatian:
Automatic translation of quantum circuits to optimized one-way quantum computation patterns. Quantum Inf. Process. 13(11): 2463-2482 (2014) - [i7]Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi, Mona Arabzadeh:
Decomposition of Diagonal Hermitian Quantum Gates Using Multiple-Controlled Pauli Z Gates. CoRR abs/1405.6741 (2014) - 2013
- [j18]Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi:
Depth-optimized reversible circuit synthesis. Quantum Inf. Process. 12(4): 1677-1699 (2013) - [j17]Maryam Yazdani, Morteza Saheb Zamani, Mehdi Sedighi:
A quantum physical design flow using ILP and graph drawing. Quantum Inf. Process. 12(10): 3239-3264 (2013) - [c57]Seyyed Ahmad Razavi, Morteza Saheb Zamani:
Improving bitstream compression by modifying FPGA architecture. FPGA 2013: 167-170 - [i6]Maryam Yazdani, Morteza Saheb Zamani, Mehdi Sedighi:
A Quantum Physical Design Flow Using ILP and Graph Drawing. CoRR abs/1306.2037 (2013) - 2012
- [c56]Eesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi:
OWQS: One-Way Quantum Computation Simulator. DSD 2012: 98-104 - [c55]Somayeh Kashi, Morteza Saheb Zamani:
Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of Proteins. DSD 2012: 533-536 - [c54]Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani:
Timing yield improvement of FPGAs utilizing enhanced architectures and multiple configurations under process variation (abstract only). FPGA 2012: 265 - [i5]Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi, Mehdi Saeedi:
Depth-Optimized Reversible Circuit Synthesis. CoRR abs/1208.5425 (2012) - 2011
- [j16]Ali Jahanian, Morteza Saheb Zamani, Hamid Safizadeh:
Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology. Integr. 44(2): 123-135 (2011) - [j15]Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi:
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes. Microelectron. J. 42(1): 12-20 (2011) - [j14]Mehdi Saeedi, Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi:
Block-based quantum-logic synthesis. Quantum Inf. Comput. 11(3&4): 262-277 (2011) - [j13]Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi:
Auxiliary qubit selection: a physical synthesis technique for quantum circuits. Quantum Inf. Process. 10(2): 139-154 (2011) - [c53]Seyyed Hasan Moallempour, Seyyed Ahmad Razavi, Morteza Saheb Zamani:
TSV reduction in homogeneous 3D FPGAs by logic resource and input pad replication. 3DIC 2011: 1-5 - [c52]Behzad Salami, Morteza Saheb Zamani, Ali Jahanian:
VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs. DSD 2011: 81-87 - [c51]Fatemeh Sadat Pourhashemi, Morteza Saheb Zamani:
Evaluation of FPGA routing architectures under process variation. ACM Great Lakes Symposium on VLSI 2011: 351-354 - 2010
- [j12]Ali Jahanian, Morteza Saheb Zamani:
Early Buffer Planning with Congestion Control Using Buffer Requirement Map. J. Circuits Syst. Comput. 19(5): 949-973 (2010) - [j11]Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian:
Reversible circuit synthesis using a cycle-based approach. ACM J. Emerg. Technol. Comput. Syst. 6(4): 13:1-13:26 (2010) - [j10]Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani:
A library-based synthesis methodology for reversible logic. Microelectron. J. 41(4): 185-194 (2010) - [j9]Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani:
Quantum physical synthesis: Improving physical design by netlist modifications. Microelectron. J. 41(4): 219-230 (2010) - [c50]Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi:
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs. ASP-DAC 2010: 832-837 - [c49]Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani:
Rule-based optimization of reversible circuits. ASP-DAC 2010: 849-854 - [c48]Hassan Ebrahimi, Morteza Saheb Zamani, Seyyed Ahmad Razavi:
A Switch Box Architecture to Mitigate Bridging and Short Faults in SRAM-Based FPGAs. DFT 2010: 218-224 - [c47]Delasa Aghamirzaie, Seyyed Ahmad Razavi, Morteza Saheb Zamani, Mahdi Nabiyouni:
Reduction of process variation effect on FPGAs using multiple configurations. VLSI-SoC 2010: 85-90 - [i4]Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani:
A Library-Based Synthesis Methodology for Reversible Logic. CoRR abs/1004.1697 (2010) - [i3]Mona Arabzadeh, Mehdi Saeedi, Morteza Saheb Zamani:
Rule-Based Optimization of Reversible Circuits. CoRR abs/1004.1755 (2010) - [i2]Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi, Zahra Sasanian:
Reversible Circuit Synthesis Using a Cycle-Based Approach. CoRR abs/1004.4320 (2010) - [i1]Mehdi Saeedi, Mona Arabzadeh, Morteza Saheb Zamani, Mehdi Sedighi:
Block-based quantum-logic synthesis. CoRR abs/1011.2159 (2010)
2000 – 2009
- 2009
- [c46]Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan:
A tileable switch module architecture for homogeneous 3D FPGAs. 3DIC 2009: 1-4 - [c45]Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani:
A cycle-based synthesis algorithm for reversible logic. ASP-DAC 2009: 745-750 - [c44]Naser MohammadZadeh, Minoo Mirsaeedi, Ali Jahanian, Morteza Saheb Zamani:
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network. DATE 2009: 833-838 - [c43]Naser MohammadZadeh, Morteza Saheb Zamani, Mehdi Sedighi:
Improving Latency of Quantum Circuits by Gate Exchanging. DSD 2009: 67-73 - [c42]Ali Jahanian, Morteza Saheb Zamani:
Improved performance and yield with chip master planning design methodology. ACM Great Lakes Symposium on VLSI 2009: 185-190 - 2008
- [j8]Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani:
Synthesis of reversible circuits using a moving forward strategy. IEICE Electron. Express 5(17): 638-643 (2008) - [j7]Hamid Fadishei, Mehdi Saeedi, Morteza Saheb Zamani:
A fast IP routing lookup architecture for multi-gigabit switching routers based on reconfigurable systems. Microprocess. Microsystems 32(4): 223-233 (2008) - [j6]Ali Jahanian, Morteza Saheb Zamani:
Using metro-on-chip in physical design flow for congestion and routability improvement. Microelectron. J. 39(2): 261-274 (2008) - [j5]Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani:
An architecture framework for an adaptive extensible processor. J. Supercomput. 45(3): 313-340 (2008) - [c41]Arash Mehdizadeh, Morteza Saheb Zamani:
Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits. AICCSA 2008: 61-68 - [c40]Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi:
Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms. ASP-DAC 2008: 83-88 - [c39]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami:
Design space exploration for a coarse grain accelerator. ASP-DAC 2008: 685-690 - [c38]Ali Jahanian, Morteza Saheb Zamani, Mostafa Rezvani, Mehrdad Najibi:
Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability. CSICC 2008: 689-696 - [c37]Arash Mehdizadeh, Morteza Saheb Zamani:
A Novel Crosstalk Estimator after Placement. CSICC 2008: 934-937 - [c36]Ali Jahanian, Morteza Saheb Zamani:
Performance and Timing Yield Enhancement using Highway-on-Chip Planning. DSD 2008: 165-172 - [c35]Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi:
Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm. DSD 2008: 472-479 - [c34]Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani:
Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. DSD 2008: 490-493 - [c33]Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi:
An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty. DSD 2008: 558-565 - [c32]Ehsan K. Ardestani, Morteza Saheb Zamani, Mehdi Sedighi:
A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. DSD 2008: 803-806 - [c31]Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb Zamani:
Performance Improvement of Physical Retiming with Shortcut Insertion. ISVLSI 2008: 215-220 - [c30]Arash Mehdizadeh, Morteza Saheb Zamani, Hosein Shafiei:
An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme. ISVLSI 2008: 233-238 - [c29]Mahdi Aminian, Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi:
FPGA-Based Circuit Model Emulation of Quantum Algorithms. ISVLSI 2008: 399-404 - [c28]Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi:
Simultaneous Gate Sizing and Skew Scheduling to Statistical Yield Improvement. ISVLSI 2008: 467-470 - [c27]Yasaman Sanaee, Mehdi Saeedi, Morteza Saheb Zamani:
Shared-PPRM: A Memory-Efficient Representation for Boolean Reversible Functions. ISVLSI 2008: 471-474 - 2007
- [j4]Ali Jahanian, Morteza Saheb Zamani:
Metro-on-chip: an efficient physical design technique for congestion reduction. IEICE Electron. Express 4(16): 510-516 (2007) - [j3]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami:
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs. IEICE Trans. Inf. Syst. 90-D(12): 1956-1966 (2007) - [j2]Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian:
Evaluation, prediction and reduction of routing congestion. Microelectron. J. 38(8-9): 942-958 (2007) - [c26]Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi:
Algebraic Characterization of CNOT-Based Quantum Circuits with its Applications on Logic Synthesis. DSD 2007: 339-346 - [c25]Hamid Reza Kheirabadi, Morteza Saheb Zamani:
An efficient net ordering algorithm for buffer insertion. ACM Great Lakes Symposium on VLSI 2007: 521-524 - [c24]Ali Jahanian, Morteza Saheb Zamani:
Improved timing closure by early buffer planning in floor-placement design flow. ACM Great Lakes Symposium on VLSI 2007: 558-563 - [c23]Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani:
A novel synthesis algorithm for reversible circuits. ICCAD 2007: 65-68 - [c22]Hamid Noori, Farhad Mehdipour, Morteza Saheb Zamani, Koji Inoue, Kazuaki J. Murakami:
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator. ICESS 2007: 249-260 - [c21]Hamid Reza Kheirabadi, Morteza Saheb Zamani, Mehdi Saeedi:
An Efficient Analytical Approach to Path-Based Buffer Insertion. ISVLSI 2007: 219-224 - [c20]Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi:
On the Behavior of Substitution-based Reversible Circuit Synthesis Algorithms: Investigation and Improvement. ISVLSI 2007: 428-436 - [c19]Arash Mehdizadeh, Behnam Ghavami, Morteza Saheb Zamani, Hossein Pedram, Farhad Mehdipour:
An efficient heterogeneous reconfigurable functional unit for an adaptive dynamic extensible processor. VLSI-SoC 2007: 151-156 - 2006
- [j1]Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi:
An integrated temporal partitioning and physical design framework for static compilation of reconfigurable computing systems. Microprocess. Microsystems 30(1): 52-62 (2006) - [c18]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Mehdi Sedighi, Koji Inoue:
An Integrated Temporal Partitioning and Mapping Framework for Handling Custom Instructions on a Reconfigurable Functional Unit. Asia-Pacific Computer Systems Architecture Conference 2006: 219-230 - [c17]Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi, Kazuaki J. Murakami, Hamid Noori:
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs. ERSA 2006: 227-230 - [c16]Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Kazuaki J. Murakami, Koji Inoue, Mehdi Sedighi:
Custom Instruction Generation Using Temporal Partitioning Techniques for a Reconfigurable Functional Unit. EUC 2006: 722-731 - [c15]Hamid Noori, Farhad Mehdipour, Kazuaki J. Murakami, Koji Inoue, Morteza Saheb Zamani:
A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor. FPL 2006: 1-4 - [c14]Farhad Mehdipour, Morteza Saheb Zamani, Hamid Reza Ahmadifar, Mehdi Sedighi, Kazuaki J. Murakami:
Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework. IPDPS 2006 - [c13]Mehdi Saeedi, Morteza Saheb Zamani, Ali Jahanian:
Prediction and reduction of routing congestion. ISPD 2006: 72-77 - [c12]Ali Jahanian, Morteza Saheb Zamani:
Multi-Level Buffer Block Planning and Buffer Insertion for Large Design Circuits. ISVLSI 2006: 411-415 - 2005
- [c11]Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabaei:
A novel reconfigurable hardware architecture for IP address lookup. ANCS 2005: 81-90 - [c10]Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi:
Reducing Inter-Configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems. DSD 2005: 372-378 - [c9]Arash Hariri, Reza Rastegar, Keivan Navi, Morteza Saheb Zamani, Mohammad Reza Meybodi:
Cellular Learning Automata based Evolutionary Computing (CLA-EC) for Intrinsic Hardware Evolution. Evolvable Hardware 2005: 294-297 - [c8]Arash Hariri, Reza Rastegar, Morteza Saheb Zamani, Mohammad Reza Meybodi:
Parallel Hardware Implementation of Cellular Learning Automata Based Evolutionary Computing (CLA-EC) on FPGA. FCCM 2005: 311-314 - [c7]Ali Valizadeh, Morteza Saheb Zamani, Babak Sadeghian, Farhad Mehdipour:
A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms. FPT 2005: 307-308 - 2003
- [c6]Morteza Saheb Zamani, Masoud Soleimani:
Rectilinear floorplanning of FPGAs using Kohonen map. IJCNN 2003: 1163-1167
1990 – 1999
- 1999
- [c5]Morteza Saheb Zamani, Farhad Mehdipour:
An efficient method for placement of VLSI designs with Kohonen map. IJCNN 1999: 3328-3331 - 1995
- [c4]Morteza Saheb Zamani, Graham R. Hellestrand:
A neural network approach to the placement problem. ASP-DAC 1995 - [c3]Morteza Saheb Zamani, Graham R. Hellestrand:
Placement with self-organising neural networks. ICNN 1995: 2185-2189 - [c2]Morteza Saheb Zamani, Graham R. Hellestrand:
A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement and Routing of Hierarchical Designs. ISCAS 1995: 49-52 - [c1]Morteza Saheb Zamani, Graham R. Hellestrand:
A New Neural Network Approach to the Floorplanning of Hierarchical VLSI Designs. IWANN 1995: 1128-1134
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