A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. - Chun, Ki Chul; Chu, Yonggyu; Heo, Jin-Seok; Kim, Tae-Sung; Kim, Soohwan; Yang, Hui-Kap; Kim, Mi-Jo; Lee, Chang-Kyo; Kim, Ju-Hwan; Yoon, Hyunchul; Shin, Chang-Ho; Cha, Sang-uhn; et al. (2018)

A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. - Bae, Yong-Cheol; Park, Joon-Young; Rhee, Sang Jae; Ko, Seung-Bum; Jeong, Yonggwon; Noh, Kwang-Sook; Son, Young Hoon; Youn, Jaeyoun; Chu, Yonggyu; Cho, Hyunyoon; Kim, Mijo; Yim, Daesik; et al. (2012)

A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications. - Kim, Mi-Jo; Kim, Lee-Sup (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

100MHz-to-1GHz open-loop ADDLL with fast lock-time for mobile applications. - Kim, Mi-Jo; Kim, Lee-Sup (2010)

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array. - Kim, Jung-Sik; Nam, Kyung-Woo; Oh, Chi Sung; Sohn, Han Gu; Lee, Donghyuk; Kim, Sooyoung; Park, Jong-Wook; Kim, Yongjun; Kim, Mi-Jo; Kim, Jin-Guk; Lee, Hocheol; Kwon, Jinhyoung; et al. (IEEE J. Solid State Circuits, 2008)