Baobab Merkle Tree for Efficient Secure Memory. - Thomas, Samuel; Workneh, Kidus; Ishimwe, Ange-Thierry; McKevitt, Zack; Curlin, Phaedra S.; Bahar, R. Iris; Izraelevitz, Joseph; Lehman, Tamara (IEEE Comput. Archit. Lett., 2024)

A Midsummer Night's Tree: Efficient and High Performance Secure SCM. - Thomas, Samuel; Workneh, Kidus; McCarty, Jac; Izraelevitz, Joseph; Lehman, Tamara; Bahar, R. Iris (2024)

Invited: Using Causal Information to Enable More Efficient Robot Operation. - Basu, Semanti; Tatlidil, Semir; Kim, Moon Hwan; Sloman, Steven A.; Bahar, R. Iris (2024)

LipoPose: Adapting Cellpose to Lipid Nanoparticle Segmentation. - Basu, Semanti; Bajcsy, Peter; Cleveland, Thomas E., IV; Carrasco, Manuel J.; Bahar, R. Iris (2023)

Hardware Acceleration of Nonparametric Belief Propagation for Efficient Robot Manipulation. - Liu, Yanqi; Opipari, Anthony; Guérin, Théo; Bahar, Ruth Iris (2022)

Towards Hardware Accelerated Garbage Collection with Near-Memory Processing. - Thomas, Samuel; Choe, Jiwon; Gordon, Ofir; Petrank, Erez; Moreshet, Tali; Herlihy, Maurice; Bahar, R. Iris (2022)

A Reconfigurable Hardware Library for Robot Scene Perception. - Liu, Yanqi; Opipari, Anthony; Jenkins, Odest Chadwicke; Bahar, R. Iris (2022)

EDAML 2022 Invited Speaker 3: Scalable ML Architectures for Real-time Energy-efficient Computing. - Bahar, R. Iris (2022)

Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing. - Nelson, Casey; Izraelevitz, Joseph; Bahar, R. Iris; Lehman, Tamara Silbergleit (2022)

HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures. - Choe, Jiwon; Crotty, Andrew; Moreshet, Tali; Herlihy, Maurice; Bahar, R. Iris (2022)

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. - Sun, Yi; Jiang, Hui; Ramakrishnan, Lakshmi; Dworak, Jennifer; Nepal, Kundan; Manikas, Theodore W.; Bahar, R. Iris (2021)

Using Human-Guided Causal Knowledge for More Generalized Robot Task Planning. - Tatlidil, Semir; Liu, Yanqi; Sheetz, Emily; Bahar, R. Iris; Sloman, Steven A. (CoRR, 2021)

Voltage Noise Mitigation With Barrier Approximation. - Chowdhury, Zamshed I.; Khatamifard, S. Karen; Zheng, Zhaoyong; Moreshet, Tali; Bahar, R. Iris; Karpuzcu, Ulya R. (IEEE Comput. Archit. Lett., 2020)

Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation. - Liu, Yanqi; Calderoni, Giuseppe; Bahar, Ruth Iris (2020)

Hardware Acceleration of Robot Scene Perception Algorithms. - Liu, Yanqi; Derman, Can Eren; Calderoni, Giuseppe; Bahar, R. Iris (2020)

Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond. - Bahar, R. Iris; Jones, Alex K.; Katkoori, Srinivas; Madden, Patrick H.; Marculescu, Diana; Markov, Igor L. (CoRR, 2020)

Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation. - Liu, Yanqi; Calderoni, Giuseppe; Bahar, R. Iris (CoRR, 2020)

Conference Reports: Recap of the 37th Edition of the International Conference on Computer-Aided Design (ICCAD 2018). - Bahar, R. Iris (IEEE Des. Test, 2019)

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. - Sun, Yi; Zhang, Fanchen; Jiang, Hui; Nepal, Kundan; Dworak, Jennifer; Manikas, Theodore W.; Bahar, R. Iris (J. Electron. Test., 2019)

Automated High-Level Generation of Low-Power Approximate Computing Circuits. - Nepal, Kumud; Hashemi, Soheil; Tann, Hokchhay; Bahar, R. Iris; Reda, Sherief (IEEE Trans. Emerg. Top. Comput., 2019)

IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM. - Papagiannopoulou, Dimitra; Whang, Sungseob; Moreshet, Tali; Bahar, R. Iris (2019)

Energy-efficient and Sustainable Computing across the Hardware/Software Stack. - Bahar, Iris (2019)

Test Architecture for Fine Grained Capture Power Reduction. - Sun, Yi; Jiang, Hui; Ramakrishnan, Lakshmi; Segal, Matan; Nepal, Kundan; Dworak, Jennifer; Manikas, Theodore W.; Bahar, R. Iris (2019)

Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis. - Chowdhury, Zamshed I.; Khatamifard, S. Karen; Zheng, Zhaoyong; Moreshet, Tali; Bahar, R. Iris; Karpuzcu, Ulya R. (2019)

GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments. - Chen, Xiaotong; Chen, Rui; Sui, Zhiqiang; Ye, Zhefan; Liu, Yanqi; Bahar, R. Iris; Jenkins, Odest Chadwicke (2019)

Attacking memory-hard scrypt with near-data-processing. - Choe, Jiwon; Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (2019)

Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation. - Choe, Jiwon; Huang, Amy; Moreshet, Tali; Herlihy, Maurice; Bahar, R. Iris (2019)

Special Session: Does Approximation Make Testing Harder (or Easier)? - Bahar, R. Iris; Karpuzcu, Ulya R.; Misailovic, Sasa (2019)

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2019, Providence, RI, USA, April 13-17, 2019 (ACM, 2019)

GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments. - Chen, Xiaotong; Chen, Rui; Sui, Zhiqiang; Ye, Zhefan; Liu, Yanqi; Bahar, R. Iris; Jenkins, Odest Chadwicke (CoRR, 2019)

Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD). - Parameswaran, Sri; Bahar, R. Iris; Pan, David Z. (IEEE Des. Test, 2018)

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures. - Papagiannopoulou, Dimitra; Marongiu, Andrea; Moreshet, Tali; Benini, Luca; Herlihy, Maurice; Bahar, R. Iris (Int. J. Parallel Program., 2018)

Towards the Simulation Based Design and Validation of Mobile Robotic Cyber-Physical Systems. - Harris, Christopher B.; Bahar, R. Iris (J. Low Power Electron., 2018)

A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling. - Donato, Marco; Bahar, R. Iris; Patterson, William R.; Zaslavsky, Alexander (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Robust object estimation using generative-discriminative inference for secure robotics applications. - Liu, Yanqi; Costantini, Alessandro; Bahar, R. Iris; Sui, Zhiqiang; Ye, Zhefan; Lu, Shiyang; Jenkins, Odest Chadwicke (2018)

Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018 (ACM, 2018)

Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency. - Papagiannopoulou, Dimitra; Marongiu, Andrea; Moreshet, Tali; Herlihy, Maurice; Bahar, R. Iris (ACM Trans. Embed. Comput. Syst., 2017)

Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. - Tann, Hokchhay; Hashemi, Soheil; Bahar, R. Iris; Reda, Sherief (2017)

Understanding the impact of precision quantization on the accuracy and energy of neural networks. - Hashemi, Soheil; Anthony, Nicholas; Tann, Hokchhay; Bahar, R. Iris; Reda, Sherief (2017)

Evaluating critical bits in arithmetic operations due to timing violations. - Whang, Sungseob; Rachford, Tymani; Papagiannopoulou, Dimitra; Moreshet, Tali; Bahar, R. Iris (2017)

Comprehensive comparison of gradient-based cross-spectral stereo matching generated disparity maps. - Picardo, Christopher B.; Delva, Justin G. R.; Bahar, R. Iris (2017)

A Research Tool for the Power and Performance Analysis of Sensor-Based Mobile Robots. - Harris, Christopher B.; Bahar, R. Iris (2017)

Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. - Tann, Hokchhay; Hashemi, Soheil; Bahar, Iris; Reda, Sherief (CoRR, 2017)

Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. - Carle, Thomas; Papagiannopoulou, Dimitra; Moreshet, Tali; Marongiu, Andrea; Herlihy, Maurice; Bahar, R. Iris (2016)

Runtime configurable deep neural networks for energy-accuracy trade-off. - Tann, Hokchhay; Hashemi, Soheil; Bahar, R. Iris; Reda, Sherief (2016)

A fast simulator for the analysis of sub-threshold thermal noise transients. - Donato, Marco; Bahar, R. Iris; Patterson, William R.; Zaslavsky, Alexander (2016)

A low-power dynamic divider for approximate applications. - Hashemi, Soheil; Bahar, R. Iris; Reda, Sherief (2016)

Hardware acceleration of feature detection and description algorithms on low-power embedded platforms. - Ulusel, Onur; Picardo, Christopher B.; Harris, Christopher B.; Reda, Sherief; Bahar, R. Iris (2016)

Design of Error-Resilient Logic Gates with Reinforcement Using Implications. - Han, Xijing; Donato, Marco; Bahar, R. Iris; Zaslavsky, Alexander; Patterson, William R. (2016)

Using Existing Reconfigurable Logic in 3D Die Stacks for Test. - Zhang, Fanchen; Sun, Yi; Shen, Xi; Nepal, Kundan; Dworak, Jennifer; Manikas, Theodore W.; Gui, Ping; Bahar, R. Iris; Crouch, Al; Potter, John C. (2016)

Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off. - Tann, Hokchhay; Hashemi, Soheil; Bahar, R. Iris; Reda, Sherief (CoRR, 2016)

Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks. - Hashemi, Soheil; Anthony, Nicholas; Tann, Hokchhay; Bahar, R. Iris; Reda, Sherief (CoRR, 2016)

Repairing a 3-D Die-Stack Using Available Programmable Logic. - Nepal, Kundan; Alhelaly, Soha; Dworak, Jennifer; Bahar, R. Iris; Manikas, Theodore W.; Guikundan, Ping (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems. - Papagiannopoulou, Dimitra; Capodanno, Giuseppe; Moreshet, Tali; Herlihy, Maurice; Bahar, R. Iris (ACM Trans. Embed. Comput. Syst., 2015)

Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems. - Bahar, R. Iris; Jones, Alex K.; Xie, Yuan (ACM Trans. Design Autom. Electr. Syst., 2015)

Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution. - Papagiannopoulou, Dimitra; Marongiu, Andrea; Moreshet, Tali; Benini, Luca; Herlihy, Maurice; Bahar, R. Iris (2015)

A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits. - Donato, Marco; Bahar, R. Iris; Patterson, William R.; Zaslavsky, Alexander (2015)

DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications. - Hashemi, Soheil; Bahar, R. Iris; Reda, Sherief (2015)

Message from the program co-chairs. - Wang, Jun; Bahar, Iris (2015)

Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators. - Ulusel, Onur; Nepal, Kumud; Bahar, R. Iris; Reda, Sherief (ACM Trans. Reconfigurable Technol. Syst., 2014)

ABACUS: A technique for automated behavioral synthesis of approximate computing circuits. - Nepal, Kumud; Li, Yueting; Bahar, R. Iris; Reda, Sherief (2014)

Speculative synchronization for coherence-free embedded NUMA architectures. - Papagiannopoulou, Dimitra; Moreshet, Tali; Marongiu, Andrea; Benini, Luca; Herlihy, Maurice; Bahar, R. Iris (2014)

Built-in Self-Repair in a 3D die stack using programmable logic. - Nepal, Kundan; Shen, Xi; Dworak, Jennifer; Manikas, Theodore W.; Bahar, R. Iris (2013)

Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. - Papagiannopoulou, Dimitra; Bahar, R. Iris; Moreshet, Tali; Herlihy, Maurice; Marongiu, Andrea; Benini, Luca (2013)

Flexible data allocation for scratch-pad memories to reduce NBTI effects. - Papagiannopoulou, Dimitra; Prasertsom, Patipan; Bahar, R. Iris (2013)

"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation. - Bahar, R. Iris; Jones, Alex K.; Katkoori, Srinivas; Madden, Patrick H.; Marculescu, Diana; Markov, Igor L. (2013)

NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. - Ferri, Cesare; Papagiannopoulou, Dimitra; Bahar, R. Iris; Calimera, Andrea (J. Electron. Test., 2012)

Using implications to choose tests through suspect fault identification. - Dworak, Jennifer; Nepal, Kundan; Alves, Nuno; Shi, Yiwen; Imbriglia, Nicholas; Bahar, R. Iris (ACM Trans. Design Autom. Electr. Syst., 2012)

High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System. - Le, Roto; Mundy, Joseph L.; Bahar, R. Iris (2012)

Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. - Nepal, Kumud; Ulusel, Onur; Bahar, R. Iris; Reda, Sherief (2012)

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic. - Donato, Marco; Cremona, Fabio; Jin, Warren; Bahar, R. Iris; Patterson, William R.; Zaslavsky, Alexander; Mundy, Joseph L. (2012)

Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems. - Tadesse, Desta; Bahar, R. Iris; Grodstein, Joel (J. Electron. Test., 2011)

SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs. - Ferri, Cesare; Marongiu, Andrea; Lipton, Benjamin; Bahar, R. Iris; Moreshet, Tali; Benini, Luca; Herlihy, Maurice (2011)

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. - Alves, Nuno; Shi, Yiwen; Imbriglia, Nicholas; Dworak, Jennifer; Nepal, Kundan; Bahar, R. Iris (2011)

NBTI-aware data allocation strategies for scratchpad memory based embedded systems. - Ferri, Cesare; Papagiannopoulou, Dimitra; Bahar, R. Iris; Calimera, Andrea (2011)

A novel parallel Tier-1 coder for JPEG2000 using GPUs. - Le, Roto; Bahar, R. Iris; Mundy, Joseph L. (2011)

Enhancing online error detection through area-efficient multi-site implications. - Alves, Nuno; Shi, Yiwen; Dworak, Jennifer; Bahar, R. Iris; Nepal, Kundan (2011)

Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems. - Ferri, Cesare; Wood, Samantha; Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (J. Parallel Distributed Comput., 2010)

Dual-Vt assignment policies in ITD-aware synthesis. - Calimera, Andrea; Bahar, R. Iris; Macii, Enrico; Poncino, Massimo (Microelectron. J., 2010)

A Cost Effective Approach for Online Error Detection Using Invariant Relationships. - Alves, Nuno; Buben, Alison; Nepal, Kundan; Dworak, Jennifer; Bahar, R. Iris (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. - Calimera, Andrea; Bahar, R. Iris; Macii, Enrico; Poncino, Massimo (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Improving the testability and reliability of sequential circuits with invariant logic. - Alves, Nuno; Nepal, Kundan; Dworak, Jennifer; Bahar, R. Iris (2010)

Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. - Jannaty, Pooya; Sabou, Florian C.; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (2010)

Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems. - Ferri, Cesare; Wood, Samantha; Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (2010)

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010 (ACM, 2010)

2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, USA, June 17-18, 2010 (IEEE Computer Society, 2010)

Introduction to special section: Best of NANOARCH 2008. - Bahar, R. Iris (ACM J. Emerg. Technol. Comput. Syst., 2009)

Detecting errors using multi-cycle invariance information. - Alves, Nuno; Nepal, Kundan; Dworak, Jennifer; Bahar, R. Iris (2009)

High-performance, cost-effective heterogeneous 3D FPGA architectures. - Le, Roto; Reda, Sherief; Bahar, R. Iris (2009)

Energy-optimal synchronization primitives for single-chip multi-processors. - Ferri, Cesare; Bahar, R. Iris; Loghi, Mirko; Poncino, Massimo (2009)

High-performance, cost-effective heterogeneous 3D FPGA architectures. - Le, Roto; Reda, Sherief; Bahar, R. Iris (2009)

Compacting test vector sets via strategic use of implications. - Alves, Nuno; Dworak, Jennifer; Bahar, R. Iris; Nepal, Kundan (2009)

Reducing the leakage and timing variability of 2D ICcs using 3D ICs. - Reda, Sherief; Si, Aung; Bahar, R. Iris (2009)

AutoRex: An automated post-silicon clock tuning tool. - Tadesse, Desta; Grodstein, Joel; Bahar, R. Iris (2009)

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009 (ACM, 2009)

Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. - Bahar, R. Iris; Chakrabarty, Krishnendu (ACM J. Emerg. Technol. Comput. Syst., 2008)

Parametric yield management for 3D ICs: Models and strategies for improvement. - Ferri, Cesare; Reda, Sherief; Bahar, R. Iris (ACM J. Emerg. Technol. Comput. Syst., 2008)

Thermal-Aware Design Techniques for Nanometer CMOS Circuits. - Calimera, Andrea; Duraisami, Karthik; Sathanur, Ashoka Visweswara; Sithambaram, Prassanna; Bahar, R. Iris; Macii, Alberto; Macii, Enrico; Poncino, Massimo (J. Low Power Electron., 2008)

Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. - Bahar, R. Iris; Chakrabarty, Krishnendu (ACM Trans. Design Autom. Electr. Syst., 2008)

Temperature-insensitive synthesis using multi-vt libraries. - Calimera, Andrea; Macii, Enrico; Poncino, Massimo; Bahar, R. Iris (2008)

Energy efficient synchronization techniques for embedded architectures. - Ferri, Cesare; Viescas, Amber; Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (2008)

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. - Calimera, Andrea; Bahar, R. Iris; Macii, Enrico; Poncino, Massimo (2008)

Using Implications for Online Error Detection. - Nepal, Kundan; Alves, Nuno; Dworak, Jennifer; Bahar, R. Iris (2008)

Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. - Tadesse, Desta; Bahar, R. Iris; Grodstein, Joel (2008)

Architectures for Silicon Nanoelectronics and Beyond. - Bahar, R. Iris; Hammerstrom, Dan W.; Harlow, Justin E., III; Joyner, William H., Jr.; Lau, Clifford; Marculescu, Diana; Orailoglu, Alex; Pedram, Massoud (Computer, 2007)

Designing Nanoscale Logic Circuits Based on Markov Random Fields. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (J. Electron. Test., 2007)

A hardware/software framework for supporting transactional memory in a MPSoC environment. - Ferri, Cesare; Moreshet, Tali; Bahar, R. Iris; Benini, Luca; Herlihy, Maurice (SIGARCH Comput. Archit. News, 2007)

Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (2007)

Accurate timing analysis using SAT and pattern-dependent delay models. - Tadesse, Desta; Sheffield, D.; Lenge, E.; Bahar, R. Iris; Grodstein, Joel (2007)

Strategies for improving the parametric yield and profits of 3D ICs. - Ferri, Cesare; Reda, Sherief; Bahar, R. Iris (2007)

Thermally-induced soft errors in nanoscale CMOS circuits. - Li, Hua; Mundy, Joseph L.; Patterson, William R.; Kazazis, Dimitrios; Zaslavsky, Alexander; Bahar, R. Iris (2007)

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (IEEE Micro, 2006)

Timing analysis for full-custom circuits using symbolic DC formulations. - Song, Hui-Yuan; Nepal, Kundan; Bahar, R. Iris; Grodstein, Joel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. - Stojanovic, Vladimir; Bahar, R. Iris; Dworak, Jennifer; Weiss, Richard (2006)

Designing MRF based error correcting circuits for memory elements. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (2006)

Optimizing noise-immune nanoscale circuits using principles of Markov random fields. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (2006)

Trends and Future Directions in Nano Structure Based Computing and Fabrication. - Bahar, R. Iris (2006)

Energy implications of multiprocessor synchronization. - Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (2006)

Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale. - Bahar, R. Iris; Tahoori, Mehdi Baradaran; Shukla, Sandeep K.; Lombardi, Fabrizio (IEEE Des. Test Comput., 2005)

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. - Bahar, R. Iris; Song, Hui-Yuan; Nepal, Kundan; Grodstein, Joel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Designing logic circuits for probabilistic computation in the presence of noise. - Nepal, Kundan; Bahar, R. Iris; Mundy, Joseph L.; Patterson, William R.; Zaslavsky, Alexander (2005)

Energy reduction in multiprocessor systems using transactional memory. - Moreshet, Tali; Bahar, R. Iris; Herlihy, Maurice (2005)

A low-power in-order/out-of-order issue queue. - Bai, Yu; Bahar, R. Iris (ACM Trans. Archit. Code Optim., 2004)

Effects of speculation on performance and issue queue design. - Moreshet, Tali; Bahar, R. Iris (IEEE Trans. Very Large Scale Integr. Syst., 2004)

RESTA: a robust and extendable symbolic timing analysis tool. - Nepal, Kundan; Song, Hui-Yuan; Bahar, R. Iris; Grodstein, Joel (2004)

Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm. - Bai, Yu; Bahar, R. Iris (2004)

Fetch Halting on Critical Load Misses. - Mehta, Nikil; Singer, Brian; Bahar, R. Iris; Leuchtenburg, Michael; Weiss, Richard S. (2004)

Combining Software and Hardware Monitoring for Improved Power and Performance Tuning. - Chi, Eric; Salem, A. Michael; Bahar, R. Iris; Weiss, Richard S. (2003)

Power-aware issue queue design for speculative instructions. - Moreshet, Tali; Bahar, R. Iris (2003)

A Probabilistic-Based Design Methodology for Nanoscale Computation. - Bahar, R. Iris; Mundy, Joseph L.; Chen, Jie (2003)

Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. - Song, Hui-Yuan; Bohidar, S.; Bahar, R. Iris; Grodstein, Joel (2003)

A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. - Bai, Yu; Bahar, R. Iris (2003)

Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. - Song, Hui-Yuan; Bahar, R. Iris; Grodstein, Joel (2002)

Power and energy reduction via pipeline balancing. - Bahar, R. Iris; Manne, Srilatha (2001)

Power optimization of technology-dependent circuits based on symbolic computation of logic implications. - Bahar, R. Iris; Lampe, Ernest T.; Macii, Enrico (ACM Trans. Design Autom. Electr. Syst., 2000)

Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors. - Maro, Roberto; Bai, Yu; Bahar, R. Iris (2000)

A comparison of software code reordering and victim buffers. - Bahar, R. Iris; Calder, Brad; Grunwald, Dirk (SIGARCH Comput. Archit. News, 1999)

The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. - Fisk, Brian R.; Bahar, R. Iris (1999)

Power and performance tradeoffs using various caching strategies. - Bahar, R. Iris; Albera, Gianluca; Manne, Srilatha (1998)

Algebraic Decision Diagrams and Their Applications. - Bahar, R. Iris; Frohm, Erica A.; Gaona, Charles M.; Hachtel, Gary D.; Macii, Enrico; Pardo, Abelardo; Somenzi, Fabio (Formal Methods Syst. Des., 1997)

Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. - Bahar, R. Iris; Cho, Hyunwoo; Hachtel, Gary D.; Macii, Enrico; Somenzi, Fabio (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Symbolic computation of logic implications for technology-dependent low-power synthesis. - Bahar, R. Iris; Burns, M.; Hachtel, Gary D.; Macii, Enrico; Shin, H.; Somenzi, Fabio (1996)

Computing the Maximum Power Cycles of a Sequential Circuit. - Manne, Srilatha; Pardo, Abelardo; Bahar, R. Iris; Hachtel, Gary D.; Somenzi, Fabio; Macii, Enrico; Poncino, Massimo (1995)

Boolean techniques for low power driven re-synthesis. - Bahar, R. Iris; Somenzi, Fabio (1995)

CMOS dynamic power estimation based on collapsible current source transistor modeling. - Pardo, Abelardo; Bahar, R. Iris; Manne, Srilatha; Feldmann, Peter; Hachtel, Gary D.; Somenzi, Fabio (1995)

Timing Analysis of Combinational Circuits using ADD's. - Bahar, R. Iris; Cho, Hyunwoo; Hachtel, Gary D.; Macii, Enrico; Somenzi, Fabio (1994)

An ADD-based algorithm for shortest path back-tracing of large graphs. - Bahar, R. Iris; Hachtel, Gary D.; Pardo, Abelardo; Poncino, Massimo; Somenzi, Fabio (1994)

A symbolic method to reduce power consumption of circuits containing false paths. - Bahar, R. Iris; Hachtel, Gary D.; Macii, Enrico; Somenzi, Fabio (1994)

Algebraic decision diagrams and their applications. - Bahar, R. Iris; Frohm, Erica A.; Gaona, Charles M.; Hachtel, Gary D.; Macii, Enrico; Pardo, Abelardo; Somenzi, Fabio (1993)

A 100-MHz macropipelined VAX microprocessor. - Badeau, Roy W.; Bahar, R. Iris; Bemstein, Debra; Biro, Larry L.; Bowhill, William J.; Brown, John F., III; Case, Michael A.; Castelino, Ruben W.; Cooper, Elizabeth M.; Delaney, Maureen A.; Deverell, David R.; Edmondson, John H.; et al. (IEEE J. Solid State Circuits, 1992)