Baobab Merkle Tree for Efficient Secure Memory - Samuel Thomas; Kidus Workneh; Ange-Thierry Ishimwe; Zack McKevitt; Phaedra S. Curlin; R. Iris Bahar; Joseph Izraelevitz; Tamara Lehman (IEEE Comput. Archit. Lett., 2024)

A Midsummer Night's Tree: Efficient and High Performance Secure SCM - Samuel Thomas; Kidus Workneh; Jac McCarty; Joseph Izraelevitz; Tamara Lehman; R. Iris Bahar (Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3, ASPLOS 2024, La Jolla, CA, USA, 27 April 2024- 1 May 2024, 2024)

Invited: Using Causal Information to Enable More Efficient Robot Operation - Semanti Basu; Semir Tatlidil; Moon Hwan Kim; Steven A. Sloman; R. Iris Bahar (Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024, 2024)

LipoPose: Adapting Cellpose to Lipid Nanoparticle Segmentation - Semanti Basu; Peter Bajcsy; Thomas E. Cleveland IV; Manuel J. Carrasco; R. Iris Bahar (Proceedings of the 16th International Joint Conference on Biomedical Engineering Systems and Technologies, BIOSTEC 2023, Volume 2: BIOIMAGING, Lisbon, Portugal, February 16-18, 2023, 2023)

Hardware Acceleration of Nonparametric Belief Propagation for Efficient Robot Manipulation - Yanqi Liu; Anthony Opipari; Théo Guérin; Ruth Iris Bahar (FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022 - 1 March 2022, 2022)

Towards Hardware Accelerated Garbage Collection with Near-Memory Processing - Samuel Thomas; Jiwon Choe; Ofir Gordon; Erez Petrank; Tali Moreshet; Maurice Herlihy; R. Iris Bahar (IEEE High Performance Extreme Computing Conference, HPEC 2022, Waltham, MA, USA, September 19-23, 2022, 2022)

A Reconfigurable Hardware Library for Robot Scene Perception - Yanqi Liu; Anthony Opipari; Odest Chadwicke Jenkins; R. Iris Bahar (Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022, 2022)

EDAML 2022 Invited Speaker 3: Scalable ML Architectures for Real-time Energy-efficient Computing - R. Iris Bahar (IEEE International Parallel and Distributed Processing Symposium, IPDPS Workshops 2022, Lyon, France, May 30 - June 3, 2022, 2022)

Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing - Casey Nelson; Joseph Izraelevitz; R. Iris Bahar; Tamara Silbergleit Lehman (2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), Storrs, CT, USA, September 26-27, 2022, 2022)

HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures - Jiwon Choe; Andrew Crotty; Tali Moreshet; Maurice Herlihy; R. Iris Bahar (SPAA '22: 34th ACM Symposium on Parallelism in Algorithms and Architectures, Philadelphia, PA, USA, July 11 - 14, 2022, 2022)

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits - Yi Sun; Hui Jiang; Lakshmi Ramakrishnan; Jennifer Dworak; Kundan Nepal; Theodore W. Manikas; R. Iris Bahar (IEEE International Test Conference, ITC 2021, Anaheim, CA, USA, October 10-15, 2021, 2021)

Using Human-Guided Causal Knowledge for More Generalized Robot Task Planning - Semir Tatlidil; Yanqi Liu; Emily Sheetz; R. Iris Bahar; Steven A. Sloman (CoRR, 2021)

Voltage Noise Mitigation With Barrier Approximation - Zamshed I. Chowdhury; S. Karen Khatamifard; Zhaoyong Zheng; Tali Moreshet; R. Iris Bahar; Ulya R. Karpuzcu (IEEE Comput. Archit. Lett., 2020)

Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation - Yanqi Liu; Giuseppe Calderoni; Ruth Iris Bahar (30th International Conference on Field-Programmable Logic and Applications, FPL 2020, Gothenburg, Sweden, August 31 - September 4, 2020, 2020)

Hardware Acceleration of Robot Scene Perception Algorithms - Yanqi Liu; Can Eren Derman; Giuseppe Calderoni; R. Iris Bahar (IEEE/ACM International Conference On Computer Aided Design, ICCAD 2020, San Diego, CA, USA, November 2-5, 2020, 2020)

Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond - R. Iris Bahar; Alex K. Jones; Srinivas Katkoori; Patrick H. Madden; Diana Marculescu; Igor L. Markov (CoRR, 2020)

Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation - Yanqi Liu; Giuseppe Calderoni; R. Iris Bahar (CoRR, 2020)

Conference Reports: Recap of the 37th Edition of the International Conference on Computer-Aided Design (ICCAD 2018) - R. Iris Bahar (IEEE Des. Test, 2019)

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack - Yi Sun; Fanchen Zhang; Hui Jiang; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (J. Electron. Test., 2019)

Automated High-Level Generation of Low-Power Approximate Computing Circuits - Kumud Nepal; Soheil Hashemi; Hokchhay Tann; R. Iris Bahar; Sherief Reda (IEEE Trans. Emerg. Top. Comput., 2019)

IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM - Dimitra Papagiannopoulou; Sungseob Whang; Tali Moreshet; R. Iris Bahar (Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019, 2019)

Energy-efficient and Sustainable Computing across the Hardware/Software Stack - Iris Bahar (Tenth International Green and Sustainable Computing Conference, IGSC 2019, Alexandria, VA, USA, October 21-24, 2019, 2019)

Test Architecture for Fine Grained Capture Power Reduction - Yi Sun; Hui Jiang; Lakshmi Ramakrishnan; Matan Segal; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019, 2019)

Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis - Zamshed I. Chowdhury; S. Karen Khatamifard; Zhaoyong Zheng; Tali Moreshet; R. Iris Bahar; Ulya R. Karpuzcu (IEEE International Symposium on Workload Characterization, IISWC 2019, Orlando, FL, USA, November 3-5, 2019, 2019)

GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments - Xiaotong Chen; Rui Chen; Zhiqiang Sui; Zhefan Ye; Yanqi Liu; R. Iris Bahar; Odest Chadwicke Jenkins (2019 IEEE/RSJ International Conference on Intelligent Robots and Systems, IROS 2019, Macau, SAR, China, November 3-8, 2019, 2019)

Attacking memory-hard scrypt with near-data-processing - Jiwon Choe; Tali Moreshet; R. Iris Bahar; Maurice Herlihy (Proceedings of the International Symposium on Memory Systems, MEMSYS 2019, Washington, DC, USA, September 30 - October 03, 2019, 2019)

Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation - Jiwon Choe; Amy Huang; Tali Moreshet; Maurice Herlihy; R. Iris Bahar (The 31st ACM on Symposium on Parallelism in Algorithms and Architectures, SPAA 2019, Phoenix, AZ, USA, June 22-24, 2019, 2019)

Special Session: Does Approximation Make Testing Harder (or Easier)? - R. Iris Bahar; Ulya R. Karpuzcu; Sasa Misailovic (37th IEEE VLSI Test Symposium, VTS 2019, Monterey, CA, USA, April 23-25, 2019, 2019)

Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2019, Providence, RI, USA, April 13-17, 2019 - Iris Bahar; Maurice Herlihy; Emmett Witchel; Alvin R. Lebeck (ACM, 2019)

GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments - Xiaotong Chen; Rui Chen; Zhiqiang Sui; Zhefan Ye; Yanqi Liu; R. Iris Bahar; Odest Chadwicke Jenkins (CoRR, 2019)

Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD) - Sri Parameswaran; R. Iris Bahar; David Z. Pan (IEEE Des. Test, 2018)

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures - Dimitra Papagiannopoulou; Andrea Marongiu; Tali Moreshet; Luca Benini; Maurice Herlihy; R. Iris Bahar (Int. J. Parallel Program., 2018)

Towards the Simulation Based Design and Validation of Mobile Robotic Cyber-Physical Systems - Christopher B. Harris; R. Iris Bahar (J. Low Power Electron., 2018)

A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling - Marco Donato; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Robust object estimation using generative-discriminative inference for secure robotics applications - Yanqi Liu; Alessandro Costantini; R. Iris Bahar; Zhiqiang Sui; Zhefan Ye; Shiyang Lu; Odest Chadwicke Jenkins (Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018, 2018)

Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018 - Iris Bahar (ACM, 2018)

Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency - Dimitra Papagiannopoulou; Andrea Marongiu; Tali Moreshet; Maurice Herlihy; R. Iris Bahar (ACM Trans. Embed. Comput. Syst., 2017)

Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks - Hokchhay Tann; Soheil Hashemi; R. Iris Bahar; Sherief Reda (Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017, 2017)

Understanding the impact of precision quantization on the accuracy and energy of neural networks - Soheil Hashemi; Nicholas Anthony; Hokchhay Tann; R. Iris Bahar; Sherief Reda (Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, 2017)

Evaluating critical bits in arithmetic operations due to timing violations - Sungseob Whang; Tymani Rachford; Dimitra Papagiannopoulou; Tali Moreshet; R. Iris Bahar (2017 IEEE High Performance Extreme Computing Conference, HPEC 2017, Waltham, MA, USA, September 12-14, 2017, 2017)

Comprehensive comparison of gradient-based cross-spectral stereo matching generated disparity maps - Christopher B. Picardo; Justin G. R. Delva; R. Iris Bahar (IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017, 2017)

A Research Tool for the Power and Performance Analysis of Sensor-Based Mobile Robots - Christopher B. Harris; R. Iris Bahar (New Generation of CAS, NGCAS 2017, Genova, Italy, September 6-9, 2017, 2017)

Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks - Hokchhay Tann; Soheil Hashemi; Iris Bahar; Sherief Reda (CoRR, 2017)

Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems - Thomas Carle; Dimitra Papagiannopoulou; Tali Moreshet; Andrea Marongiu; Maurice Herlihy; R. Iris Bahar (2016 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2016, Pittsburgh, Pennsylvania, USA, October 1-7, 2016, 2016)

Runtime configurable deep neural networks for energy-accuracy trade-off - Hokchhay Tann; Soheil Hashemi; R. Iris Bahar; Sherief Reda (Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES 2016, Pittsburgh, Pennsylvania, USA, October 1-7, 2016, 2016)

A fast simulator for the analysis of sub-threshold thermal noise transients - Marco Donato; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky (Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016, 2016)

A low-power dynamic divider for approximate applications - Soheil Hashemi; R. Iris Bahar; Sherief Reda (Proceedings of the 53rd Annual Design Automation Conference, DAC 2016, Austin, TX, USA, June 5-9, 2016, 2016)

Hardware acceleration of feature detection and description algorithms on low-power embedded platforms - Onur Ulusel; Christopher B. Picardo; Christopher B. Harris; Sherief Reda; R. Iris Bahar (26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016, 2016)

Design of Error-Resilient Logic Gates with Reinforcement Using Implications - Xijing Han; Marco Donato; R. Iris Bahar; Alexander Zaslavsky; William R. Patterson (Proceedings of the 26th edition on Great Lakes Symposium on VLSI, GLVLSI 2016, Boston, MA, USA, May 18-20, 2016, 2016)

Using Existing Reconfigurable Logic in 3D Die Stacks for Test - Fanchen Zhang; Yi Sun; Xi Shen; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; Ping Gui; R. Iris Bahar; Al Crouch; John C. Potter (25th IEEE North Atlantic Test Workshop, NATW 2016, Providence, RI, USA, May 9-11, 2016, 2016)

Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off - Hokchhay Tann; Soheil Hashemi; R. Iris Bahar; Sherief Reda (CoRR, 2016)

Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks - Soheil Hashemi; Nicholas Anthony; Hokchhay Tann; R. Iris Bahar; Sherief Reda (CoRR, 2016)

Repairing a 3-D Die-Stack Using Available Programmable Logic - Kundan Nepal; Soha Alhelaly; Jennifer Dworak; R. Iris Bahar; Theodore W. Manikas; Ping Guikundan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems - Dimitra Papagiannopoulou; Giuseppe Capodanno; Tali Moreshet; Maurice Herlihy; R. Iris Bahar (ACM Trans. Embed. Comput. Syst., 2015)

Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems - R. Iris Bahar; Alex K. Jones; Yuan Xie (ACM Trans. Design Autom. Electr. Syst., 2015)

Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution - Dimitra Papagiannopoulou; Andrea Marongiu; Tali Moreshet; Luca Benini; Maurice Herlihy; R. Iris Bahar (Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015, 2015)

A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits - Marco Donato; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky (Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015, 2015)

DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications - Soheil Hashemi; R. Iris Bahar; Sherief Reda (Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Austin, TX, USA, November 2-6, 2015, 2015)

Message from the program co-chairs - Jun Wang; Iris Bahar (10th IEEE International Conference on Networking, Architecture and Storage, NAS 2015, Boston, MA, USA, August 6-7, 2015, 2015)

Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators - Onur Ulusel; Kumud Nepal; R. Iris Bahar; Sherief Reda (ACM Trans. Reconfigurable Technol. Syst., 2014)

ABACUS: A technique for automated behavioral synthesis of approximate computing circuits - Kumud Nepal; Yueting Li; R. Iris Bahar; Sherief Reda (Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014)

Speculative synchronization for coherence-free embedded NUMA architectures - Dimitra Papagiannopoulou; Tali Moreshet; Andrea Marongiu; Luca Benini; Maurice Herlihy; R. Iris Bahar (XIVth International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2014, Agios Konstantinos, Samos, Greece, July 14-17, 2014, 2014)

Built-in Self-Repair in a 3D die stack using programmable logic - Kundan Nepal; Xi Shen; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013, 2013)

Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs - Dimitra Papagiannopoulou; R. Iris Bahar; Tali Moreshet; Maurice Herlihy; Andrea Marongiu; Luca Benini (Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, MES'2013, Held in conjunction with the 40th Annual IEEE/ACM International Symposium on Computer Architecture, ISCA 2013, June 24, 2013, 2013)

Flexible data allocation for scratch-pad memories to reduce NBTI effects - Dimitra Papagiannopoulou; Patipan Prasertsom; R. Iris Bahar (International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013, 2013)

"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation - R. Iris Bahar; Alex K. Jones; Srinivas Katkoori; Patrick H. Madden; Diana Marculescu; Igor L. Markov (2013 IEEE International Conference on Microelectronic Systems Education, MSE 2013, Austin, TX, USA, June 2-3, 2013, 2013)

NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems - Cesare Ferri; Dimitra Papagiannopoulou; R. Iris Bahar; Andrea Calimera (J. Electron. Test., 2012)

Using implications to choose tests through suspect fault identification - Jennifer Dworak; Kundan Nepal; Nuno Alves; Yiwen Shi; Nicholas Imbriglia; R. Iris Bahar (ACM Trans. Design Autom. Electr. Syst., 2012)

High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System - Roto Le; Joseph L. Mundy; R. Iris Bahar (23rd IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012, Delft, The Netherlands, July 9-11, 2012, 2012)

Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators - Kumud Nepal; Onur Ulusel; R. Iris Bahar; Sherief Reda (2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012, 29 April - 1 May 2012, Toronto, Ontario, Canada, 2012)

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic - Marco Donato; Fabio Cremona; Warren Jin; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky; Joseph L. Mundy (Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake City, UT, USA, May 3-4, 2012, 2012)

Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems - Desta Tadesse; R. Iris Bahar; Joel Grodstein (J. Electron. Test., 2011)

SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs - Cesare Ferri; Andrea Marongiu; Benjamin Lipton; R. Iris Bahar; Tali Moreshet; Luca Benini; Maurice Herlihy (Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2011, part of ESWeek '11 Seventh Embedded Systems Week, Taipei, Taiwan, 9-14 October, 2011, 2011)

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis - Nuno Alves; Yiwen Shi; Nicholas Imbriglia; Jennifer Dworak; Kundan Nepal; R. Iris Bahar (16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011, 2011)

NBTI-aware data allocation strategies for scratchpad memory based embedded systems - Cesare Ferri; Dimitra Papagiannopoulou; R. Iris Bahar; Andrea Calimera (12th Latin American Test Workshop, LATW 2011, Beach of Porto de Galinhas, Brazil, March 27-30, 2011, 2011)

A novel parallel Tier-1 coder for JPEG2000 using GPUs - Roto Le; R. Iris Bahar; Joseph L. Mundy (IEEE 9th Symposium on Application Specific Processors, SASP 2011, San Diego, CA, USA, June 5-6, 2011, 2011)

Enhancing online error detection through area-efficient multi-site implications - Nuno Alves; Yiwen Shi; Jennifer Dworak; R. Iris Bahar; Kundan Nepal (29th IEEE VLSI Test Symposium, VTS 2011, May 1-5, 2011, Dana Point, California, USA, 2011)

Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems - Cesare Ferri; Samantha Wood; Tali Moreshet; R. Iris Bahar; Maurice Herlihy (J. Parallel Distributed Comput., 2010)

Dual-V\(_t\) assignment policies in ITD-aware synthesis - Andrea Calimera; R. Iris Bahar; Enrico Macii; Massimo Poncino (Microelectron. J., 2010)

A Cost Effective Approach for Online Error Detection Using Invariant Relationships - Nuno Alves; Alison Buben; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Temperature-Insensitive Dual- V\(_th\) Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence - Andrea Calimera; R. Iris Bahar; Enrico Macii; Massimo Poncino (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Improving the testability and reliability of sequential circuits with invariant logic - Nuno Alves; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, 2010)

Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices - Pooya Jannaty; Florian C. Sabou; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, 2010)

Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems - Cesare Ferri; Samantha Wood; Tali Moreshet; R. Iris Bahar; Maurice Herlihy (High Performance Embedded Architectures and Compilers, 5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings, 2010)

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010 - R. Iris Bahar; Fabrizio Lombardi; David Atienza; Erik Brunvand (ACM, 2010)

2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010, Anaheim, CA, USA, June 17-18, 2010 - Shamik Das; Iris Bahar; Michael T. Niemier (IEEE Computer Society, 2010)

Introduction to special section: Best of NANOARCH 2008 - R. Iris Bahar (ACM J. Emerg. Technol. Comput. Syst., 2009)

Detecting errors using multi-cycle invariance information - Nuno Alves; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009, 2009)

High-performance, cost-effective heterogeneous 3D FPGA architectures - Roto Le; Sherief Reda; R. Iris Bahar (Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, 2009)

Energy-optimal synchronization primitives for single-chip multi-processors - Cesare Ferri; R. Iris Bahar; Mirko Loghi; Massimo Poncino (Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009)

High-performance, cost-effective heterogeneous 3D FPGA architectures - Roto Le; Sherief Reda; R. Iris Bahar (Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, 2009)

Compacting test vector sets via strategic use of implications - Nuno Alves; Jennifer Dworak; R. Iris Bahar; Kundan Nepal (2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009, 2009)

Reducing the leakage and timing variability of 2D ICcs using 3D ICs - Sherief Reda; Aung Si; R. Iris Bahar (Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, 2009)

AutoRex: An automated post-silicon clock tuning tool - Desta Tadesse; Joel Grodstein; R. Iris Bahar (2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009, 2009)

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009 - Fabrizio Lombardi; Sanjukta Bhanja; Yehia Massoud; R. Iris Bahar (ACM, 2009)

Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies - R. Iris Bahar; Krishnendu Chakrabarty (ACM J. Emerg. Technol. Comput. Syst., 2008)

Parametric yield management for 3D ICs: Models and strategies for improvement - Cesare Ferri; Sherief Reda; R. Iris Bahar (ACM J. Emerg. Technol. Comput. Syst., 2008)

Thermal-Aware Design Techniques for Nanometer CMOS Circuits - Andrea Calimera; Karthik Duraisami; Ashoka Visweswara Sathanur; Prassanna Sithambaram; R. Iris Bahar; Alberto Macii; Enrico Macii; Massimo Poncino (J. Low Power Electron., 2008)

Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies - R. Iris Bahar; Krishnendu Chakrabarty (ACM Trans. Design Autom. Electr. Syst., 2008)

Temperature-insensitive synthesis using multi-vt libraries - Andrea Calimera; Enrico Macii; Massimo Poncino; R. Iris Bahar (Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, 2008)

Energy efficient synchronization techniques for embedded architectures - Cesare Ferri; Amber Viescas; Tali Moreshet; R. Iris Bahar; Maurice Herlihy (Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, 2008)

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits - Andrea Calimera; R. Iris Bahar; Enrico Macii; Massimo Poncino (Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008, 2008)

Using Implications for Online Error Detection - Kundan Nepal; Nuno Alves; Jennifer Dworak; R. Iris Bahar (2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008, 2008)

Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation - Desta Tadesse; R. Iris Bahar; Joel Grodstein (26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, 2008)

Architectures for Silicon Nanoelectronics and Beyond - R. Iris Bahar; Dan W. Hammerstrom; Justin E. Harlow III; William H. Joyner Jr.; Clifford Lau; Diana Marculescu; Alex Orailoglu; Massoud Pedram (Computer, 2007)

Designing Nanoscale Logic Circuits Based on Markov Random Fields - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (J. Electron. Test., 2007)

A hardware/software framework for supporting transactional memory in a MPSoC environment - Cesare Ferri; Tali Moreshet; R. Iris Bahar; Luca Benini; Maurice Herlihy (SIGARCH Comput. Archit. News, 2007)

Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, 2007)

Accurate timing analysis using SAT and pattern-dependent delay models - Desta Tadesse; D. Sheffield; E. Lenge; R. Iris Bahar; Joel Grodstein (2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, 2007)

Strategies for improving the parametric yield and profits of 3D ICs - Cesare Ferri; Sherief Reda; R. Iris Bahar (2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, 2007)

Thermally-induced soft errors in nanoscale CMOS circuits - Hua Li; Joseph L. Mundy; William R. Patterson; Dimitrios Kazazis; Alexander Zaslavsky; R. Iris Bahar (2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH 2007, San Jose, CA, USA, October 21-22, 2007, 2007)

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (IEEE Micro, 2006)

Timing analysis for full-custom circuits using symbolic DC formulations - Hui-Yuan Song; Kundan Nepal; R. Iris Bahar; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors - Vladimir Stojanovic; R. Iris Bahar; Jennifer Dworak; Richard Weiss (Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, 2006)

Designing MRF based error correcting circuits for memory elements - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, 2006)

Optimizing noise-immune nanoscale circuits using principles of Markov random fields - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006, 2006)

Trends and Future Directions in Nano Structure Based Computing and Fabrication - R. Iris Bahar (24th International Conference on Computer Design (ICCD 2006), 1-4 October 2006, San Jose, CA, USA, 2006)

Energy implications of multiprocessor synchronization - Tali Moreshet; R. Iris Bahar; Maurice Herlihy (SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30 - August 2, 2006, 2006)

Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale - R. Iris Bahar; Mehdi Baradaran Tahoori; Sandeep K. Shukla; Fabrizio Lombardi (IEEE Des. Test Comput., 2005)

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing - R. Iris Bahar; Hui-Yuan Song; Kundan Nepal; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Designing logic circuits for probabilistic computation in the presence of noise - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, 2005)

Energy reduction in multiprocessor systems using transactional memory - Tali Moreshet; R. Iris Bahar; Maurice Herlihy (Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, 2005)

A low-power in-order/out-of-order issue queue - Yu Bai; R. Iris Bahar (ACM Trans. Archit. Code Optim., 2004)

Effects of speculation on performance and issue queue design - Tali Moreshet; R. Iris Bahar (IEEE Trans. Very Large Scale Integr. Syst., 2004)

RESTA: a robust and extendable symbolic timing analysis tool - Kundan Nepal; Hui-Yuan Song; R. Iris Bahar; Joel Grodstein (Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, 2004)

Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm - Yu Bai; R. Iris Bahar (22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, 2004)

Fetch Halting on Critical Load Misses - Nikil Mehta; Brian Singer; R. Iris Bahar; Michael Leuchtenburg; Richard S. Weiss (22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, 2004)

Combining Software and Hardware Monitoring for Improved Power and Performance Tuning - Eric Chi; A. Michael Salem; R. Iris Bahar; Richard S. Weiss (7th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7 2003), 8 February 2003, Anaheim, CA, USA, 2003)

Power-aware issue queue design for speculative instructions - Tali Moreshet; R. Iris Bahar (Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, 2003)

A Probabilistic-Based Design Methodology for Nanoscale Computation - R. Iris Bahar; Joseph L. Mundy; Jie Chen (2003 International Conference on Computer-Aided Design, ICCAD 2003, San Jose, CA, USA, November 9-13, 2003, 2003)

Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current - Hui-Yuan Song; S. Bohidar; R. Iris Bahar; Joel Grodstein (21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, 2003)

A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors - Yu Bai; R. Iris Bahar (2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, 2003)

Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations - Hui-Yuan Song; R. Iris Bahar; Joel Grodstein (11th IEEE/ACM International Workshop on Logic & Synthesis, IWLS 2002, June 4-7, 2002, New Orleans, Louisiana, USA, 2002)

Power and energy reduction via pipeline balancing - R. Iris Bahar; Srilatha Manne (Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001, 2001)

Power optimization of technology-dependent circuits based on symbolic computation of logic implications - R. Iris Bahar; Ernest T. Lampe; Enrico Macii (ACM Trans. Design Autom. Electr. Syst., 2000)

Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors - Roberto Maro; Yu Bai; R. Iris Bahar (Power-Aware Computer Systems, First International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, 2000)

A comparison of software code reordering and victim buffers - R. Iris Bahar; Brad Calder; Dirk Grunwald (SIGARCH Comput. Archit. News, 1999)

The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency - Brian R. Fisk; R. Iris Bahar (Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, 1999)

Power and performance tradeoffs using various caching strategies - R. Iris Bahar; Gianluca Albera; Srilatha Manne (Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, 1998)

Algebraic Decision Diagrams and Their Applications - R. Iris Bahar; Erica A. Frohm; Charles M. Gaona; Gary D. Hachtel; Enrico Macii; Abelardo Pardo; Fabio Somenzi (Formal Methods Syst. Des., 1997)

Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths - R. Iris Bahar; Hyunwoo Cho; Gary D. Hachtel; Enrico Macii; Fabio Somenzi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Symbolic computation of logic implications for technology-dependent low-power synthesis - R. Iris Bahar; M. Burns; Gary D. Hachtel; Enrico Macii; H. Shin; Fabio Somenzi (Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996, 1996)

Computing the Maximum Power Cycles of a Sequential Circuit - Srilatha Manne; Abelardo Pardo; R. Iris Bahar; Gary D. Hachtel; Fabio Somenzi; Enrico Macii; Massimo Poncino (Proceedings of the 32st Conference on Design Automation, San Francisco, California, USA, Moscone Center, June 12-16, 1995, 1995)

Boolean techniques for low power driven re-synthesis - R. Iris Bahar; Fabio Somenzi (Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, 1995)

CMOS dynamic power estimation based on collapsible current source transistor modeling - Abelardo Pardo; R. Iris Bahar; Srilatha Manne; Peter Feldmann; Gary D. Hachtel; Fabio Somenzi (Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995, 1995)

Timing Analysis of Combinational Circuits using ADD's - R. Iris Bahar; Hyunwoo Cho; Gary D. Hachtel; Enrico Macii; Fabio Somenzi (EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France, 1994)

An ADD-based algorithm for shortest path back-tracing of large graphs - R. Iris Bahar; Gary D. Hachtel; Abelardo Pardo; Massimo Poncino; Fabio Somenzi (Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, GLSV '94, Notre Dame, IN, USA, March 4-5, 1994, 1994)

A symbolic method to reduce power consumption of circuits containing false paths - R. Iris Bahar; Gary D. Hachtel; Enrico Macii; Fabio Somenzi (Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, 1994)

Algebraic decision diagrams and their applications - R. Iris Bahar; Erica A. Frohm; Charles M. Gaona; Gary D. Hachtel; Enrico Macii; Abelardo Pardo; Fabio Somenzi (Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993, Santa Clara, California, USA, November 7-11, 1993, 1993)

A 100-MHz macropipelined VAX microprocessor - Roy W. Badeau; R. Iris Bahar; Debra Bemstein; Larry L. Biro; William J. Bowhill; John F. Brown III; Michael A. Case; Ruben W. Castelino; Elizabeth M. Cooper; Maureen A. Delaney; David R. Deverell; John H. Edmondson; et al. (IEEE J. Solid State Circuits, 1992)