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ORCIDYukihiko Shimazu
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2020 – today
- 2024
[c6]Hiroshi Miyata, Kazutami Arimoto, Masatoshi Saitoh, Atsushi Hayami, Hisayoshi Mizuno, Yukihiko Shimazu, Tomoyuki Yokogawa:
Distributed Hierarchical AI Architecture for Meta-Described Local Dynamic Maps in Autonomous Driving. IIAI-AAI 2024: 595-600
2000 – 2009
- 2007
- [j2]Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu:
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. IEEE J. Solid State Circuits 42(1): 183-192 (2007) - 2006
- [c5]Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu:
A 40GOPS 250mW massively parallel processor based on matrix architecture. ISSCC 2006: 1616-1625
1990 – 1999
- 1996
- [c4]Mamoru Sakamoto, Toyohiko Yoshida, Yasuhiro Nunomura, Yukihiko Shimazu:
Microarchitecture Support for Reducing Branch Penalty in a Supercscaler Processor. ICCD 1996: 208-216 - 1993
- [c3]Eiichi Teraoka, Toru Kengaku, Ikuo Yasui, Kazuyuki Ishikawa, Takahiro Matsuo, Hideyuki Wakada, Narumi Sakashita, Yukihiko Shimazu, Takeshi Tokuda:
A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC. ITC 1993: 791-796 - 1990
- [c2]Narumi Sakashita, Hisako Sawai, Eiichi Teraoka, Toshiki Fugiyama, Toru Kengaku, Yukihiko Shimazu, Takeshi Tokuda:
Built-in self-test in a 24 bit floating point digital signal processor. ITC 1990: 880-885
1980 – 1989
- 1988
- [j1]Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa:
A macrocell approach for VLSI processor design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(12): 1272-1277 (1988) - 1986
- [c1]Shingo Tsujimichi, TakaHide Ohkami, Yukihiko Shimazu:
A next-generation 32-bit VLSI signal processor. ICASSP 1986: 413-416
Coauthor Index
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