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ORCIDHiroyuki Tomiyama
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- affiliation: Ritsumeikan University, Department of Electronic and Computer Engineering
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2020 – today
- 2024
[j76]Juncheng Wang
, Xiangbo Kong, Hiroki Nishikawa, Qiuyou Lian, Hiroyuki Tomiyama:
Dynamic Point-Pixel Feature Alignment for Multimodal 3-D Object Detection. IEEE Internet Things J. 11(7): 11327-11340 (2024)- [c130]Genki Higashiuchi, Tomoyasu Shimada, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Evaluation of Self-localization Estimation in Indoor Environments Using Cameras for Small Drones. ATAIT 2024: 93-103 - [c129]Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
Simultaneous Routing with Washing Droplets in MEDA Biochips. ATAIT 2024: 190-201 - [c128]Hiroki Matsumiya, Xiangbo Kong, Ami Tanaka, Hiroki Nishikawa, Hiroyuki Tomiyama:
Spin Estimation for Back Spin Serves in Table Tennis Using Racket Speed and Angle. ICEIC 2024: 1-3 - [c127]Yuto Miura, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Impacts of Clock Frequency and Sampling Intervals on Power Side-Channel Leakage of AES Circuits. ICEIC 2024: 1-2 - [c126]Mao Nishira, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Multi-Trip Routing of Delivery Drones with Load-Dependent Flight Speed. ICEIC 2024: 1-4 - [c125]Wakana Ohashi, Aoi Yamaguch, Hiroki Nishikawa, Hiroyuki Tomiyama:
Fast 32-bit and 48-bit Multipliers for FPGA. ICEIC 2024: 1-3 - [c124]Tomoki Shimizu, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
A Non-Work Conserving Algorithm for Dynamic Scheduling of Moldable Gang Tasks on Multicore Systems. ICEIC 2024: 1-4 - 2023
- [j75]Hengyi Li, Zhichen Wang, Xuebin Yue, Wenwen Wang, Hiroyuki Tomiyama, Lin Meng:
An architecture-level analysis on deep learning models for low-impact computations. Artif. Intell. Rev. 56(3): 1971-2010 (2023) - [j74]Junichi Kurihara, Toru Nagata, Hiroyuki Tomiyama:
Rice Yield Prediction in Different Growth Environments Using Unmanned Aerial Vehicle-Based Hyperspectral Imaging. Remote. Sens. 15(8): 2004 (2023) - [j73]Tomohisa Kawakami, Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
A Deep Reinforcement Learning Approach to Droplet Routing for Erroneous Digital Microfluidic Biochips. Sensors 23(21): 8924 (2023) - [c123]Taosong Zhao, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Design and Evaluation of AES Encryption Circuits with Various S-Box Implementation. ATAIT 2023: 48-53 - [c122]Ruisheng Xu, Ami Tanaka, Xiangbo Kong, Hiroyuki Tomiyama:
Ball Touching Net Detection Using Piezoelectric Element in Table Tennis. ATAIT 2023: 90-98 - [c121]Yuta Fujihara, Xiangbo Kong, Ami Tanaka, Hiroki Nishikawa, Hiroyuki Tomiyama:
In/Out Judgement by Ball Tracking in Table Tennis. ATAIT 2023: 115-126 - [c120]Takuto Maejima, Xiangbo Kong, Tomoyasu Shimada, Hiroki Nishikawa, Hiroyuki Tomiyama:
Drone path planning method to reduce energy consumption. ATAIT 2023: 127-137 - [c119]Takuya Kosaka, Xiangbo Kong, Tomoyasu Shimada, Hiroki Nishikawa, Hiroyuki Tomiyama:
Faster Depth Estimation for Autonomous Flying Drones. ATAIT 2023: 138-146 - [c118]Yuto Miura, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Simulation-based Analysis of Power Side-Channel Leakage at Different Sampling Intervals. CANDARW 2023: 364-365 - [c117]Kaito Mori, Mao Nishira, Hiroki Nishikawa, Hiroyuki Tomiyama:
Surveillance Routing with a Minimum Number of Drones. CANDARW 2023: 366-367 - [c116]Yuto Miura, Takumi Mizuno, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Impacts of Clock Constraints on Side-Channel Leakage of HLS-designed AES Circuits. ICEIC 2023: 1-2 - [c115]Takumi Mizuno, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Empirical Analysis of Side-Channel Attack Resistance of HLS-designed AES Circuits. ICEIC 2023: 1-4 - [c114]Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
Multi-Droplet Routing based on a Shape-Dependent Velocity Model on MEDA Biochips. ICEIC 2023: 1-4 - [c113]Tomohisa Kawakami, Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
A Deep Reinforcement Learning-based Routing Algorithm for Unknown Erroneous Cells in DMFBs. NEWCAS 2023: 1-5 - [c112]Kaito Mori, Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
A Fast Approach to Droplet Routing with Shape-Dependent Velocity on MEDA Biochips. NEWCAS 2023: 1-5 - [c111]Hiroshi Yamada, Ting He, Hiroyuki Tomiyama, Nan Guan, Sebastian Steinhorst:
Message from the Chairs: RTCSA 2023. RTCSA 2023: xi - [c110]Masataka Hirai, Debraj Kundu, Shigeru Yamashita, Sudip Roy, Hiroyuki Tomiyama:
Transport-Free Placement of Mixers for Realizing Bioprotocol on Programmable Microfluidic Devices. VLSID 2023: 193-198 - 2022
- [j72]Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, Sudip Roy:
Shape-Dependent Velocity Based Droplet Routing on MEDA Biochips. IEEE Access 10: 122423-122430 (2022) - [j71]Koyu Ohata, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
ILP-Based and Heuristic Scheduling Techniques for Variable-Cycle Approximate Functional Units in High-Level Synthesis. Comput. 11(10): 146 (2022) - [j70]Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Simultaneous Scheduling and Core-Type Optimization for Moldable Fork-Join Tasks on Heterogeneous Multicores. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 540-548 (2022) - [j69]Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Mouldable fork-join task scheduling techniques with inter and intra-task communications. Int. J. Embed. Syst. 15(1): 69-81 (2022) - [j68]Tomoyasu Shimada, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Pix2Pix-Based Monocular Depth Estimation for Drones with Optical Flow on AirSim. Sensors 22(6): 2097 (2022) - [c109]Hiroki Matsumiya, Xiangbo Kong, Ami Tanaka, Hiroki Nishikawa, Hiroyuki Tomiyama:
A Case Study on Forehand Footwork Mistake Detection in Table Tennis. ATAIT 2022: 7-16 - [c108]Mao Nishira, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Delivery Drone Routing under Load-dependent Flight Speed based on Integer Quadratic Programming. ATAIT 2022: 35-42 - [c107]Tomoyasu Shimada, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Monocular Thermal Camera Depth Estimation with Optical Flow for Autonomous Drones. ATAIT 2022: 43-52 - [c106]Koyu Ohata, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
A Heuristic Scheduling Algorithm with Variable-Cycle Approximate Functional Units in High-Level Synthesis. ATAIT 2022: 53-59 - [c105]Masaki Sano, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato:
An Accuracy-Controllable Approximate Adder for FPGAs. ATAIT 2022: 60-66 - [c104]Yilin Zhao, Qidi Zhang, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Evaluation of Power Analysis Attack Resistance of Masked Adders on FPGA. ATAIT 2022: 67-74 - [c103]Mao Nishira, Satoshi Ito, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
An ILP-based Approach to Delivery Drone Routing under Load-dependent Flight Speed. ICEIC 2022: 1-4 - [c102]Tomoyasu Shimada, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Depth Estimation from Monocular Infrared Images for Autonomous Flight of Drones. ICEIC 2022: 1-6 - [c101]Jo Yoshimoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Takao Onoye:
Priority-aware Static Task Mapping for Edge-Cloud Platforms. ICEIC 2022: 1-4 - [c100]Eiji Sugahara, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Energy Consumption Reduction through Resource Allocation Using Docker. CANDARW 2022: 436-437 - [c99]Tomoyasu Shimhada, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Monocular Depth Estimation with Optical Flow Attention for Autonomous Drones. ISOCC 2022: 197-198 - [c98]Wanyin Shi, Hiroki Matsumiya, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Fusing Infrared and Visible Images for DNN-based Nighttime Human Detection. ISOCC 2022: 203-204 - [c97]Tomoki Shimizu, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
A Fair-Policy Dynamic Scheduling Algorithm for Moldable Gang Tasks on Multicores. MECO 2022: 1-4 - [c96]Yuho Toku, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Container-based Throughput Balancing for Multiple Streaming Applications: A Case Study. MECO 2022: 1-4 - 2021
- [j67]Satoshi Ito, Hiroki Nishikawa, Xiangbo Kong, Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Energy-aware Routing of Delivery Drones under Windy Conditions. IPSJ Trans. Syst. LSI Des. Methodol. 14: 30-39 (2021) - [c95]Tomoyasu Shimada, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Pix2Pix-Based Depth Estimation from Monocular Images for Dynamic Path Planning of Multirotor on AirSim. ATAIT 2021: 1-9 - [c94]Zelin Meng, Lin Meng, Kenshi Saho, Xiangbo Kong, Hiroyuki Tomiyama:
Frailty Classification Based on Artificial Intelligence. ATAIT 2021: 99-107 - [c93]Satoshi Ito, Keishi Akaiwa, Yusuke Funabashi, Hiroki Nishikawa, Xiangbo Kong, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Routing of Delivery Drones Considering Load and Wind Effects. ATAIT 2021: 116-125 - [c92]Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
Minimization of Routing Area in MEDA Biochips. BioCAS 2021: 1-5 - [c91]Takuya Egashira, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
A Home Security Camera System with Container-based Resource Allocation on Raspberry Pi. ICEIC 2021: 1-4 - [c90]Hengyi Li, Zhichen Wang, Xuebin Yue, Wenwen Wang, Hiroyuki Tomiyama, Lin Meng:
A Comprehensive Analysis of Low-Impact Computations in Deep Learning Workloads. ACM Great Lakes Symposium on VLSI 2021: 385-390 - [c89]Takumi Mizuno, Qidi Zhang, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Impacts of HLS Optimizations on Side-Channel Leakage for AES Circuits. ISOCC 2021: 53-54 - [c88]Masaki Sano, Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Tongxin Yang, Tomoaki Ukezono:
Design of a 32-bit Accuracy-Controllable Approximate Multiplier for FPGAs. ISOCC 2021: 55-56 - [c87]Koyu Ohata, Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Scheduling with Variable-Cycle Approximate Functional Units in High-Level Synthesis. ISOCC 2021: 57-58 - [c86]Yilin Zhao, Qidi Zhang, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
Power Side-Channel Analysis for Different Adders on FPGA. ISOCC 2021: 367-368 - [c85]Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
High-Level Synthesis of Approximate Computing Circuits with Dual Accuracy Modes. ISOCC 2021: 369-370 - 2020
- [j66]Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama:
A branch-and-bound approach to scheduling of data-parallel tasks on multi-core architectures. Int. J. Embed. Syst. 12(1): 125-135 (2020) - [j65]Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro, Ittetsu Taniguchi, Hiroyuki Tomiyama:
A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones. IPSJ Trans. Syst. LSI Des. Methodol. 13: 65-68 (2020) - [c84]Bing Lyu, Hiroyuki Tomiyama, Lin Meng:
Frame Detection and Text Line Segmentation for Early Japanese Books Understanding. ICPRAM 2020: 600-606 - [c83]Takuma Hikida, Hiroki Nishikawa, Hiroyuki Tomiyama:
Heuristic Algorithms for Dynamic Scheduling of Moldable Tasks. ISOCC 2020: 55-56 - [c82]Jo Yoshimoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Takao Onoye:
An Evaluation of Edge Computing Platform for Reliable Automated Drones. ISOCC 2020: 95-96 - [c81]Zelin Meng, Zhiyu Zhang, Lin Meng, Hiroyuki Tomiyama:
A Case Study on Rubbing Character Recognition Based on Deep Learning. ISOCC 2020: 318-319 - [c80]Takava Watanabe, Hiroki Nishikawa, Hiroyuki Tomiyama:
Scheduling of Rigid Tasks on Heterogeneous Multicores. ISOCC 2020: 330-331 - [c79]Mayu Ida, Hiroki Nishikawa, Xiangbo Kong, Ittetsu Taniguchi, Hiroyuki Tomiyama:
A Quadcopters Flight Simulation Considering the Influence of Wind. ISOCC 2020: 334-335 - [c78]Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Scheduling of moldable fork-join tasks with inter- and intra-task communications. SCOPES 2020: 7-12
2010 – 2019
- 2019
- [j64]Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
A Constraint Programming Approach to Scheduling of Malleable Tasks. Int. J. Netw. Comput. 9(2): 131-146 (2019) - [j63]Yaqiang Zhang, Lin Meng, Xiao Xue, Zhangbing Zhou, Hiroyuki Tomiyama:
QoE-Constrained Concurrent Request Optimization Through Collaboration of Edge Servers. IEEE Internet Things J. 6(6): 9951-9962 (2019) - [j62]Seiya Shirakuni, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Design and Evaluation of Asymmetric and Symmetric 32-core Architectures on FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 12: 42-45 (2019) - [j61]Takafumi Miyazaki, Shunsuke Takai, Ittetsu Taniguchi, Hiroyuki Tomiyama:
An OpenCL-based Software Framework for a Heterogeneous Multicore Architecture on Zynq-7000 SoC. IPSJ Trans. Syst. LSI Des. Methodol. 12: 46-49 (2019) - [j60]Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Communication-Aware Scheduling of Data-Parallel Tasks on Multicore Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 12: 65-73 (2019) - [j59]Yang Liu, Lin Meng, Hiroyuki Tomiyama:
A Genetic Algorithm for Scheduling of Data-parallel Tasks on Multicore Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 12: 74-77 (2019) - [j58]Xiangbo Kong, Zelin Meng, Lin Meng, Hiroyuki Tomiyama:
Three-States-Transition Method for Fall Detection Algorithm Using Depth Image. J. Robotics Mechatronics 31(1): 88-94 (2019) - [j57]Xiangbo Kong, Lehan Chen, Zhichen Wang, Yuxi Chen, Lin Meng, Hiroyuki Tomiyama:
Robust Self-Adaptation Fall-Detection System Based on Camera Height. Sensors 19(17): 3768 (2019) - [j56]Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
ILP-based scheduling for malleable fork-join tasks. SIGBED Rev. 16(3): 21-26 (2019) - [j55]Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Energy-aware scheduling of malleable fork-join tasks under a deadline constraint on heterogeneous multicores. SIGBED Rev. 16(3): 57-62 (2019) - [c77]Takuma Hikida, Yusuke Funabashi, Hiroyuki Tomiyama:
A Web-Based Routing and Visualization Tool for Drone Delivery. CANDAR Workshops 2019: 264-268 - [c76]Kana Shimada, Takuma Hikida, Hiroki Nishikawa, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Scheduling of Malleable Tasks with DMA-based Communication. ISOCC 2019: 48-49 - [c75]Ryohei Nozaki, Hiroki Nishikawa, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Function-Level Module Sharing in High-Level Synthesis. ISOCC 2019: 50-51 - [c74]Kenta Shirane, Takahiro Yamamoto, Ittetsu Taniguchi, Yuko Hara-Azumi, Shigeru Yamashita, Hiroyuki Tomiyama:
Maximum Error-Aware Design of Approximate Array Multipliers. ISOCC 2019: 73-74 - [c73]Zelin Meng, Xiangbo Kong, Lin Meng, Hiroyuki Tomiyama:
Lucas-Kanade Optical Flow Based Camera Motion Estimation Approach. ISOCC 2019: 77-78 - [c72]Yusuke Funabashi, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Work-in-Progress: Routing of Delivery Drones with Load-Dependent Flight Speed. RTSS 2019: 520-523 - 2018
- [c71]Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Communication-aware scheduling of data-parallel tasks: work-in-progress. CASES 2018: 8:1-8:2 - [c70]Seiya Shirakuni, Ittetsu Taniguchi, Hiroyuki Tomiyama:
A Case Study on Memory Architecture Exploration for Manycores on an FPGA. CANDAR Workshops 2018: 132-137 - [c69]Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Scheduling of Malleable Fork-Join Tasks with Constraint Programming. CANDAR 2018: 133-138 - [c68]Takafumi Miyazaki, Hayato Hidari, Naohisa Hojo, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Revisiting Thread Execution Methods for GPU-Oriented OpenCL Programs on Multicore Processors. CANDAR Workshops 2018: 520-523 - [c67]Xiangbo Kong, Zelin Meng, Naoto Nojiri, Yuji Iwahori, Lin Meng, Hiroyuki Tomiyama:
A HOG-SVM Based Fall Detection IoT System for Elderly Persons Using Deep Sensor. IIKI 2018: 276-282 - [c66]Yuuki Oosako, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara:
Synthesis of Full Hardware Implementation of RTOS-Based Systems. RSP 2018: 1-7 - [c65]Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Scheduling of Malleable Tasks Based on Constraint Programming. TENCON 2018: 1493-1498 - 2017
- [j54]Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi:
A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1496-1499 (2017) - [j53]Yining Xu, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Static Mapping of Parallelizable Tasks under Deadline Constraints. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1500-1502 (2017) - [j52]Kana Shimada, Shogo Kitano, Ittetsu Taniguchi, Hiroyuki Tomiyama:
ILP-Based Scheduling for Parallelizable Tasks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1503-1505 (2017) - [j51]Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama:
A dual-mode scheduling approach for task graphs with data parallelism. Int. J. Embed. Syst. 9(2): 147-156 (2017) - [c64]Kotaro Maekawa, Shunsuke Negoro, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Power Measurement and Modeling of Quadcopters on Horizontal Flight. CANDAR 2017: 326-329 - [c63]Naoya Ito, Yuuki Oosako, Nagisa Ishiura, Hiroyuki Kanbara, Hiroyuki Tomiyama:
Binary synthesis implementing external interrupt handler as independent module. RSP 2017: 92-98 - 2016
- [j50]Gang Zeng, Yutaka Matsubara, Hiroyuki Tomiyama, Hiroaki Takada:
Energy-aware task migration for multiprocessor real-time systems. Future Gener. Comput. Syst. 56: 220-228 (2016) - [j49]Yining Xu, Yang Liu, Junya Kaida, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Static Mapping of Multiple Parallel Applications on Non-Hierarchical Manycore Embedded Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(7): 1417-1419 (2016) - [c62]Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi:
A systematic methodology for design and analysis of approximate array multipliers. APCCAS 2016: 352-354 - 2015
- [j48]Tran Van Dung, Ittetsu Taniguchi, Takuji Hieda, Hiroyuki Tomiyama:
Function-level profiling for embedded software with QEMU. Int. J. Embed. Syst. 7(2): 170-179 (2015) - [j47]Hiroyuki Tomiyama:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 8: 1 (2015) - [c61]Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, Jason Helge Anderson:
Profiling-driven multi-cycling in FPGA high-level synthesis. DATE 2015: 31-36 - [c60]Naohisa Hojo, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Comparison of Thread Execution Methods for GPU-oriented OpenCL Programs on Multicore Processors. EWiLi 2015 - 2014
- [j46]Ittetsu Taniguchi, Kohei Aoki, Hiroyuki Tomiyama, Praveen Raghavan, Francky Catthoor, Masahiro Fukui:
Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(2): 606-615 (2014) - [j45]Ittetsu Taniguchi, Junya Kaida, Takuji Hieda, Yuko Hara-Azumi, Hiroyuki Tomiyama:
Static Mapping with Dynamic Switching of Multiple Data-Parallel Applications on Embedded Many-Core SoCs. IEICE Trans. Inf. Syst. 97-D(11): 2827-2834 (2014) - [j44]Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada:
An Integrated Framework for Energy Optimization of Embedded Real-Time Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2477-2487 (2014) - [j43]Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Novel List Scheduling Strategies for Data Parallelism Task Graphs. Int. J. Netw. Comput. 4(2): 279-290 (2014) - [j42]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. Inf. Media Technol. 9(1): 26-34 (2014) - [j41]Hiroyuki Tomiyama:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 7: 1 (2014) - [j40]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Impact of Resource Sharing and Register Retiming on Area and Performance of FPGA-based Designs. IPSJ Trans. Syst. LSI Des. Methodol. 7: 37-45 (2014) - [c59]Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama:
A dual-mode scheduling algorithm for task graphs with data parallelism. APCCAS 2014: 371-374 - [c58]Tran Van Dung, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Cache Simulation for Instruction Set Simulator QEMU. DASC 2014: 441-446 - [c57]Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Fast Design-Space Exploration Method for SW/HW Codesign on FPGAs. FCCM 2014: 235 - [c56]Gang Zeng, Yutaka Matsubara, Hiroyuki Tomiyama, Hiroaki Takada:
Task Migration for Energy Saving in Real-Time Multiprocessor Systems. HPCC/CSS/ICESS 2014: 685-692 - 2013
- [j39]Junya Kaida, Yuko Hara-Azumi, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Koji Inoue:
Static Mapping of Multiple Data-Parallel Applications on Embedded Many-Core SoCs. IEICE Trans. Inf. Syst. 96-D(10): 2268-2271 (2013) - [j38]Keita Nakajima, Shuto Kurebayashi, Yusuke Fukutsuka, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Hiroaki Takada:
Naxim: A Fast and Retargetable Network-on-Chip Simulator with QEMU and SystemC. Int. J. Netw. Comput. 3(2): 217-227 (2013) - [j37]Krzysztof Jozwik, Shinya Honda, Masato Edahiro, Hiroyuki Tomiyama, Hiroaki Takada:
Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs. Int. J. Reconfigurable Comput. 2013: 789134:1-789134:40 (2013) - [j36]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks. Inf. Media Technol. 8(4): 924-928 (2013) - [j35]Hiroyuki Tomiyama:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 6: 1 (2013) - [j34]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Quantitative Evaluation of Resource Sharing in High-level Synthesis Using Realistic Benchmarks. IPSJ Trans. Syst. LSI Des. Methodol. 6: 122-126 (2013) - [c55]Hiroyuki Tomiyama, Takuji Hieda, Naoki Nishiyama, Noriko Etani, Ittetsu Taniguchi:
SMYLE OpenCL: A programming framework for embedded many-core SoCs. ASP-DAC 2013: 565-567 - [c54]Yang Liu, Ittetsu Taniguchi, Hiroyuki Tomiyama, Lin Meng:
List Scheduling Strategies for Task Graphs with Data Parallelism. CANDAR 2013: 168-172 - [c53]Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Automated Identification of Performance Bottleneck on Embedded Systems for Design Space Exploration. IESS 2013: 171-180 - [c52]Yuko Hara-Azumi, Hiroyuki Tomiyama:
Cost-efficient scheduling in high-level synthesis for Soft-Error Vulnerability Mitigation. ISQED 2013: 502-507 - [c51]Tran Van Dung, Ittetsu Taniguchi, Takuji Hieda, Hiroyuki Tomiyama:
Function profiling for embedded software by utilizing QEMU and analyzer tool. MWSCAS 2013: 1251-1254 - 2012
- [j33]Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada:
Comparison of Preemption Schemes for Partially Reconfigurable FPGAs. IEEE Embed. Syst. Lett. 4(2): 45-48 (2012) - [j32]Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
A Novel Framework for Effective Preemptive Hardware Multitasking on FPGAs. IEICE Trans. Inf. Syst. 95-D(2): 345-353 (2012) - [j31]Hiroyuki Tomiyama:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 5: 1 (2012) - [j30]Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
A Fast Performance Estimation Framework for System-Level Design Space Exploration. IPSJ Trans. Syst. LSI Des. Methodol. 5: 44-54 (2012) - [c50]Yuko Hara, Hiroyuki Tomiyama:
Clock-constrained simultaneous allocation and binding for multiplexer optimization in high-level synthesis. ASP-DAC 2012: 251-256 - [c49]Yuko Hara-Azumi, Toshinobu Matsuba, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level Synthesis. HPCC-ICESS 2012: 1534-1540 - [c48]Keita Nakajima, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Hiroaki Takada:
A Fast Network-on-Chip Simulator with QEMU and SystemC. ICNC 2012: 298-301 - [c47]Mitsuya Uchida, Ittetsu Taniguchi, Hiroyuki Tomiyama, Masahiro Fukui:
Energy-aware SA-based instruction scheduling for fine-grained power-gated VLIW processors. ISOCC 2012: 139-142 - [c46]Junya Kaida, Takuji Hieda, Ittetsu Taniguchi, Hiroyuki Tomiyama, Yuko Hara-Azumi, Koji Inoue:
Task mapping techniques for embedded many-core SoCs. ISOCC 2012: 204-207 - 2011
- [j29]Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada:
Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(10): 1954-1964 (2011) - [c45]Tomohiro Tatematsu, Hideki Takase, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
Checkpoint Extraction Using Execution Traces for Intra-task DVFS in Embedded Systems. DELTA 2011: 19-24 - [c44]Ittetsu Taniguchi, Mitsuya Uchida, Hiroyuki Tomiyama, Masahiro Fukui, Praveen Raghavan, Francky Catthoor:
An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating. DSD 2011: 693-700 - [c43]Hideki Takase, Gang Zeng, Lovic Gauthier, Hirotaka Kawashima, Noritoshi Atsumi, Tomohiro Tatematsu, Yoshitake Kobayashi, Shunitsu Kohara, Takenori Koshiro, Tohru Ishihara, Hiroyuki Tomiyama, Hiroaki Takada:
An integrated optimization framework for reducing the energy consumption of embedded real-time applications. ISLPED 2011: 271-276 - [c42]Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Fast design space exploration for mixed hardware-software embedded systems. ISOCC 2011: 92-95 - [c41]Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada:
Hardware multitasking in dynamically partially reconfigurable FPGA-based embedded systems. ISOCC 2011: 183-186 - [c40]Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada:
Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs. ReConFig 2011: 416-421 - 2010
- [j28]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Partitioning of Behavioral Descriptions with Exploiting Function-Level Parallelism. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 488-499 (2010) - [j27]Tetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
Static Task Scheduling Algorithms Based on Greedy Heuristics for Battery-Powered DVS Systems. IEICE Trans. Inf. Syst. 93-D(10): 2737-2746 (2010) - [j26]Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Automatic Communication Synthesis with Hardware Sharing for Multi-Processor SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2509-2516 (2010) - [j25]Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation. Inf. Media Technol. 5(4): 1082-1096 (2010) - [j24]Seiya Shibata, Yuki Ando, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Efficient Design Space Exploration at System Level with Automatic Profiler Instrumentation. IPSJ Trans. Syst. LSI Des. Methodol. 3: 179-193 (2010) - [c39]Lovic Gauthier, Tohru Ishihara, Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada:
Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems. CASES 2010: 157-166 - [c38]Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada:
Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems. DATE 2010: 1124-1129 - [c37]Toshinobu Matsuba, Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Aggressive Register Unsharing Based on SSA Transformation for Clock Enhancement in High-Level Synthesis. DELTA 2010: 87-92 - [c36]Krzysztof Jozwik, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
A Novel Mechanism for Effective Hardware Task Preemption in Dynamically Reconfigurable Systems. FPL 2010: 352-355 - [c35]Yuki Ando, Seiya Shibata, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Automatic communication synthesis with hardware sharing for design space exploration. ISCAS 2010: 1863-1866
2000 – 2009
- 2009
- [j23]Shan Ding, Hiroyuki Tomiyama, Hiroaki Takada:
Effective Scheduling Algorithms for I/O Blocking with a Multi-Frame Task Model. IEICE Trans. Inf. Syst. 92-D(7): 1412-1420 (2009) - [j22]Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
A Generalized Framework for Energy Savings in Hard Real-Time Embedded Systems. Inf. Media Technol. 4(4): 714-726 (2009) - [j21]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. Inf. Media Technol. 4(4): 740-752 (2009) - [j20]Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada:
Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems. Inf. Media Technol. 4(4): 837-845 (2009) - [j19]Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
A Generalized Framework for Energy Savings in Hard Real-Time Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 2: 167-179 (2009) - [j18]Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada:
Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems. IPSJ Trans. Syst. LSI Des. Methodol. 2: 180-188 (2009) - [j17]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis. J. Inf. Process. 17: 242-254 (2009) - [c34]Tetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
Analyzing and optimizing energy efficiency of algorithms on DVS systems a first step towards algorithmic energy minimization. ASP-DAC 2009: 727-732 - [c33]Tetsuo Yokoyama, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
Heuristics for Static Voltage Scheduling Algorithms on Battery-Powered DVS Systems. ICESS 2009: 265-272 - [c32]Gang Zeng, Tetsuo Yokoyama, Hiroyuki Tomiyama, Hiroaki Takada:
Practical Energy-Aware Scheduling for Real-Time Multiprocessor Systems. RTCSA 2009: 383-392 - 2008
- [j16]Hideki Takase, Hiroyuki Tomiyama, Gang Zeng, Hiroaki Takada:
Energy efficiency of scratch-pad memory in deep submicron domains: an empirical study. IEICE Electron. Express 5(23): 1010-1016 (2008) - [j15]Shan Ding, Hiroyuki Tomiyama, Hiroaki Takada:
An Effective GA-Based Scheduling Algorithm for FlexRay Systems. IEICE Trans. Inf. Syst. 91-D(8): 2115-2123 (2008) - [j14]Masanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori, Hiroyuki Kanbara, Hiroyuki Tomiyama:
High-Level Synthesis of Software Function Calls. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3556-3558 (2008) - [j13]Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
Dynamic Power Management for Embedded System Idle State in the Presence of Periodic Interrupt Services. Inf. Media Technol. 3(4): 661-670 (2008) - [j12]Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada:
Embedded System Covalidation with RTOS Model and FPGA. Inf. Media Technol. 3(4): 739-743 (2008) - [j11]Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
Dynamic Power Management for Embedded System Idle State in the Presence of Periodic Interrupt Services. IPSJ Trans. Syst. LSI Des. Methodol. 1: 48-57 (2008) - [j10]Seiya Shibata, Shinya Honda, Yuko Hara, Hiroyuki Tomiyama, Hiroaki Takada:
Embedded System Covalidation with RTOS Model and FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 1: 126-130 (2008) - [c31]Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Koji Inoue:
Improved Policies for Drowsy Caches in Embedded Processors. DELTA 2008: 362-367 - [c30]Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, Tohru Ishihara:
A Generalized Framework for System-Wide Energy Savings in Hard Real-Time Embedded Systems. EUC (1) 2008: 206-213 - [c29]Hideki Takase, Hiroyuki Tomiyama, Gang Zeng, Hiroaki Takada:
Energy Efficiency of Scratch-Pad Memory at 65 nm and Below: An Empirical Study. ICESS 2008: 93-97 - [c28]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
CHStone: A benchmark program suite for practical C-based high-level synthesis. ISCAS 2008: 1192-1195 - 2007
- [j9]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Function Call Optimization for Efficient Behavioral Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(9): 2032-2036 (2007) - [j8]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
Function-Level Partitioning of Sequential Programs for Efficient Behavioral Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2853-2862 (2007) - [j7]Masaki Yamamoto, Shinya Honda, Hiroaki Takada, Kiyoshi Agusa, Hiroyuki Tomiyama, Kenji Mase, Nobuo Kawaguchi, Nobuyuki Kaneko:
Practice and analysis of an extension course for training trainers of embedded software. SIGBED Rev. 4(1): 73-81 (2007) - [c27]Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
RTOS and Codesign Toolkit for Multiprocessor Systems-on-Chip. ASP-DAC 2007: 336-341 - [c26]Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
A Software Framework for Energy and Performance Tradeoff in Fixed-Priority Hard Real-Time Embedded Systems. EUC 2007: 13-24 - [c25]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
Complexity-constrainted partitioning of sequential programs for efficient behavioral synthesis. ACM Great Lakes Symposium on VLSI 2007: 365-370 - [c24]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada, Katsuya Ishii:
Behavioral Synthesis of Double-Precision Floating-Point Adders with Function-Level Transformations: A Case Study. ICESS 2007: 261-270 - [c23]Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
A Hardware/Software Cosimulator with RTOS Supports for Multiprocessor Embedded Systems. ICESS 2007: 283-294 - [c22]Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada:
Power Optimization for Embedded System Idle Time in the Presence of Periodic Interrupt Services. IESS 2007: 241-254 - [c21]Shan Ding, Hiroyuki Tomiyama, Hiroaki Takada:
Scheduling Algorithms for I/O Blockings with a Multi-frame Task Model. RTCSA 2007: 386-393 - 2006
- [c20]Yuko Hara, Hiroyuki Tomiyama, Shinya Honda, Hiroaki Takada:
Function Call Optimization in Behavioral Synthesis. DSD 2006: 522-529 - 2005
- [j6]Hiroyuki Tomiyama, Shin-ichiro Chikada, Shinya Honda, Hiroaki Takada:
An RTOS-Based Design and Validation Methodology for Embedded Systems. IEICE Trans. Inf. Syst. 88-D(9): 2205-2208 (2005) - [j5]Masaki Yamamoto, Hiroyuki Tomiyama, Hiroaki Takada, Kiyoshi Agusa, Kenji Mase, Nobuo Kawaguchi, Shinya Honda, Nobuyuki Kaneko:
NEXCESS: Nagoya university extension courses for embedded software specialists. SIGBED Rev. 2(4): 20-24 (2005) - [c19]Shan Ding, Naohiko Murakami, Hiroyuki Tomiyama, Hiroaki Takada:
A GA-based scheduling method for FlexRay systems. EMSOFT 2005: 110-113 - [c18]Shin-ichiro Chikada, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada:
Cosimulation of ITRON-based embedded software with SystemC. HLDVT 2005: 71-76 - [c17]Hiroshi Miyamoto, Shinichi Iiyama, Hiroyuki Tomiyama, Hiroaki Takada, Hiroshi Nakashima:
An Efficient Search Algorithm of Worst-Case Cache Flush Timings. RTCSA 2005: 45-52 - 2004
- [j4]Hiroyuki Tomiyama, Nikil D. Dutt:
ILP-Based Program Path Analysis for Bounding Worst-Case Inter-Task Cache Conflicts. IEICE Trans. Inf. Syst. 87-D(6): 1582-1587 (2004) - [c16]Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada:
RTOS-centric hardware/software cosimulator for embedded system design. CODES+ISSS 2004: 158-163 - 2003
- [j3]Prabhat Mishra, Nikil D. Dutt, Hiroyuki Tomiyama:
Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications. Des. Autom. Embed. Syst. 8(2-3): 249-265 (2003) - [c15]Hiroyuki Tomiyama, Hiroaki Takada, Nikil D. Dutt:
Data Organization Exploration for Low-Energy Address Buses. ESTIMedia 2003: 128-133 - 2002
- [c14]Prabhat Mishra, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama:
Automatic Verification of In-Order Execution In Microprocessors with Fragmented Pipelines and Multicycle Functional Units. DATE 2002: 36-43 - [c13]Hiroto Yasuura, Hiroyuki Tomiyama, Takanori Okuma, Yun Cao:
Data Memory Design Considering Effective Bitwidth for Low-Energy Embedded Systems. ISSS 2002: 201-206 - [c12]Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
Automatic Modeling and Validation of Pipeline Specifications Driven by an Architecture Description Language. ASP-DAC/VLSI Design 2002: 458- - 2001
- [c11]Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama, Ashok Halambi:
New directions in compiler technology for embedded systems (embedded tutorial). ASP-DAC 2001: 409-414 - [c10]Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil D. Dutt:
Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique. VLSI Design 2001: 97-102 - 2000
- [c9]Hiroyuki Tomiyama, Nikil D. Dutt:
Program path analysis to bound cache-related preemption delay in preemptive real-time systems. CODES 2000: 67-71 - [c8]Hiroyuki Tomiyama, Taisei Yoshino, Nikil D. Dutt:
Verification of in-order execution in pipelined processors. HLDVT 2000: 40-44
1990 – 1999
- 1998
- [j2]Hiroto Yasuura, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar:
Embedded System Design Using Soft-Core Processor and Valen-C. J. Inf. Sci. Eng. 14(3): 587-603 (1998) - [c7]Hiroyuki Tomiyama, Hiroto Yasuura:
Module Selection Using Manufacturing Information. ASP-DAC 1998: 275-281 - [c6]Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura:
Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE 1998: 855-860 - [c5]Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura:
Statistical Performance-Driven Module Binding in High-Level Synthesis. ISSS 1998: 66-71 - [c4]Takanori Okuma, Hiroyuki Tomiyama, Akihiko Inoue, Eko Fajar, Hiroto Yasuura:
Instruction Encoding Techniques for Area Minimization of Instruction ROM. ISSS 1998: 125-130 - 1997
- [j1]Hiroyuki Tomiyama, Hiroto Yasuura:
Code placement techniques for cache miss rate reduction. ACM Trans. Design Autom. Electr. Syst. 2(4): 410-429 (1997) - [c3]Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Hiroto Yasuura:
Memory-CPU Size Optimization for Embedded System Designs. DAC 1997: 246-251 - 1996
- [c2]Hiroyuki Tomiyama, Hiroto Yasuura:
Optimal Code Placement of Embedded Software for Instruction Caches. ED&TC 1996: 96-101 - [c1]Hiroyuki Tomiyama, Hiroto Yasuura:
Size-Constrained Code Placement for Cache Miss Rate Reduction. ISSS 1996: 96-104
Coauthor Index
Yuko Hara-Azumi
aka: Yuko Hara
aka: Yuko Hara
[j76] [c130] [c129] [c128] [c127] [c126] [c124] [j73] [c123] [c122] [c121] [c120] [c119] [c118] [c116] [c115] [c114] [c113] [c112] [j72] [j71] [j68] [c109] [c108] [c107] [c106] [c105] [c104] [c103] [c102] [c100] [c99] [c98] [c97] [c96] [j67] [c95] [c94] [c93] [c92] [c91] [c89] [c88] [c87] [c86] [c85] [c79] [j58] [j57] [c73] [c67]
[j76] [c130] [c129] [c128] [c127] [c126] [c125] [c124] [j73] [c123] [c121] [c120] [c119] [c118] [c117] [c116] [c115] [c114] [c113] [c112] [j72] [j71] [j70] [j69] [j68] [c109] [c108] [c107] [c106] [c105] [c104] [c103] [c102] [c100] [c99] [c98] [c97] [c96] [j67] [c95] [c93] [c92] [c91] [c89] [c88] [c87] [c86] [c85] [c83] [c80] [c79] [c78] [j64] [j55] [c76] [c75] [c69] [c65]
[j50] [j44] [j42] [j40] [c57] [c56] [j38] [j37] [j36] [j34] [c53] [j33] [j32] [j30] [c49] [c48] [j29] [c45] [c43] [c42] [c41] [c40] [j28] [j27] [j26] [j25] [j24] [c39] [c38] [c37] [c36] [c35] [j23] [j22] [j21] [j20] [j19] [j18] [j17] [c34] [c33] [c32] [j16] [j15] [j13] [j12] [j11] [j10] [c31] [c30] [c29] [c28] [j9] [j8] [j7] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [j6] [j5] [c19] [c18] [c17] [c16] [c15]
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