Ultra-Thin-Body and Buried Oxide FD-SOI next generation nodes and eNVM technologies for advanced IC design. - Fenouillet-Béranger, Claire; Fesquet, Laurent; Chouk, Rihab; Pares, Gabriel; Martineau, Baudoin; Cyrille, Marie Claire; Poiroux, Thierry; Billoint, Olivier; Noguet, Dominique (2025)

Wideband Tunable N-Path Mixer With Calibrated Harmonic Rejection Including the 7th LO Harmonic. - Ibrahim, Sana; Shakoush, Ali Al; Subias, Serge; Vincent, Loic; Asian, Manuel J. Barragan; Fesquet, Laurent; Podevin, Florence; Bourdel, Sylvain (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Data-driven Processing Element for Sparse Convolutional Neural Networks. - Lesage, Xavier; Merio, Cristiano; Welzel, Fernando; Araujo, Luca Sauer de; Engels, Sylvain; Fesquet, Laurent (2024)

Time-to-Digital Converter Based Self-Timed Ring Oscillator: An FPGA Implementation. - El-Hadbi, Assia; Elissati, Oussama; Fesquet, Laurent (2024)

A New Control Law for N-Path Mixer Switches Enhancing Harmonic Rejection. - Moussa, Hasan; Lauga-Larroze, Estelle; Fesquet, Laurent (2024)

Velocity and Color Estimation Using Event-Based Clustering. - Lesage, Xavier; Tran, Rosalie; Mancini, Stéphane; Fesquet, Laurent (Sensors, 2023)

Low-Throughput Event-Based Image Sensors and Processing. - Fesquet, Laurent; Tran, Rosalie; Lesage, Xavier; Akrarai, Mohamed; Mancini, Stéphane; Sicard, Gilles (2023)

Making Digital N-Path Mixers. - Moussa, Hasan; Gonsalves, Jessica; Lauga-Larroze, Estelle; Ibrahim, Sana; Podevin, Florence; Bourdel, Sylvain; Fesquet, Laurent (2023)

A Generic CDC Modeling for Data Stability Verification. - Kalel, Diana; Brignone, Jean-Christophe; Fesquet, Laurent; Morin-Allory, Katell (2023)

Method for Data-Driven Pruning in Micropipeline Circuits. - Merio, Cristiano; Lesage, Xavier; Naimi, Ali; Engels, Sylvain; Morin-Allory, Katell; Fesquet, Laurent (2023)

An improved event-by-event clustering algorithm for noisy acquisition. - Lesage, Xavier; Tran, Rosalie; Mancini, Stéphane; Fesquet, Laurent (2022)

A Novel Event-Based Method for ASK Demodulation. - Jadue, Alexis Rodrigo Iga; Engels, Sylvain; Fesquet, Laurent (2022)

N-Path Mixer with Wide Rejection Including the 7th Harmonic for Low Power Multi-standard Receivers. - Shakoush, Ali Al; Ibrahim, Sana; Subias, Serge; Podevin, Florence; Barragán, Manuel J.; Pino-Monroy, Dayana A.; Bendjeddou, Imadeddine; Lauga-Larroze, Estelle; Fesquet, Laurent; Taris, Thierry; Bourdel, Sylvain (2022)

Self-Timed Ring Oscillators for Non-Overlapping and Overlapping Phases Synthesis. - Moussa, Hasan; Ibrahim, Sana; Lauga-Larroze, Estelle; Podevin, Florence; Bourdel, Sylvain; Fesquet, Laurent (2022)

An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits. - Belot, Jérémy; Cherkaoui, Abdelkarim; Laurent, Raphaël; Fesquet, Laurent (IEEE Des. Test, 2021)

Design and Characterization of an Asynchronous Fixed Priority Tree Arbiter for SPAD Array Readout. - Aguénounon, Enagnon; Razavinejad, Safa; Schell, Jean-Baptiste; Lakeh, Mohammadreza Dolatpoor; Khaddour, Wassim; Dadouche, Foudil; Kammerer, Jean-Baptiste; Fesquet, Laurent; Uhring, Wilfried (Sensors, 2021)

An asynchronous hybrid pixel image sensor. - Akrarai, Mohamed; Margotat, Nils; Sicard, Gilles; Fesquet, Laurent (2021)

Comparison between an ASK Event-Based Demodulation and a Digital IQ Demodulation. - Jadue, Alexis Rodrigo Iga; Engels, Sylvain; Fesquet, Laurent (2021)

Self-Timed Ring Oscillator based Time-to-Digital Converter: A 0.35μ m CMOS Proof-of-Concept Prototype. - El-Hadbi, Assia; Elissati, Oussama; Fesquet, Laurent (2021)

A hybrid event-based pixel for low-power image sensing. - Akrarai, Mohamed; Margotat, Nils; Sicard, Gilles; Fesquet, Laurent (2021)

An Energy Efficient Multi-Rail Architecture for Stochastic Computing: A Bayesian Sensor Fusion Case Study. - Belot, Jérémy; Cherkaoui, Abdelkarim; Laurent, Raphaël; Fesquet, Laurent (2021)

A High-Level Design Flow for Locally Body Biased Asynchronous Circuits. - Decoudu, Yoan; Morin-Allory, Katell; Fesquet, Laurent (2021)

Trojan Detection Test for Clockless Circuits. - Guazzelli, Ricardo Aquino; Trindade, Matheus Garay; Guimaraes, Leonel Acunha; Leite, Thiago Ferreira de Paiva; Fesquet, Laurent; Bastos, Rodrigo Possamai (J. Electron. Test., 2020)

A Self-Timed Ring based PUF. - Gimenez, Grégoire; Cherkaoui, Abdelkarim; Fesquet, Laurent (2020)

Arbiterless Event-Based Imager Architecture with temporal and spatial redundancies suppression. - Akrarai, Mohamed; Margotat, Nils; Sicard, Gilles; Fesquet, Laurent (2020)

An Effective QRS Selection Based on the Level-Crossing Sampling and Activity Selection. - Qaisar, Saeed Mian; Fesquet, Laurent (2020)

At-speed DfT Architecture for Bundled-data Design. - Guazzelli, Ricardo Aquino; Fesquet, Laurent (2020)

Improved $π$-Delayed Harmonic Rejection N-Path Mixer for Low Power Consumption and Multistandard Receiver. - Shakoush, Ali Al; Lauga-Larroze, Estelle; Podevin, Florence; Ibrahim, Sana; Fesquet, Laurent; Bourdel, Sylvain (2020)

A Novel Event Based Image Sensor with spacial and temporal redundancy suppression. - Akrarai, Mohamed; Margotat, Nils; Sicard, Gilles; Fesquet, Laurent (2020)

From High-Level Synthesis to Bundled-Data Circuits. - Decoudu, Yoan; Simatic, Jean; Morin-Allory, Katell; Fesquet, Laurent (2020)

From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits. - Gimenez, Grégoire; Simatic, Jean; Fesquet, Laurent (2019)

On-Line Adjustable Precision Computing. - Skaf, Ali; Ezzadeen, Mona; Benabdenbi, Mounir; Fesquet, Laurent (2019)

A new synthesis approach for non-uniform filters in the log-scale: Proof of concept. - Bidégaray-Fesquet, Brigitte; Fesquet, Laurent (2019)

Comparison of Synchronous and Asynchronous FIR Filter Architectures. - Decoudu, Yoan; Simatic, Jean; Alexandre, Pauline; Morin-Allory, Katell; Fesquet, Laurent (2019)

Time-to-Digital Converters: A Literature Review and New Perspectives. - El-Hadbi, Assia; Elissati, Oussama; Fesquet, Laurent (2019)

An Event-Based Strategy for ASK demodulation. - Jadue, Alexis Rodrigo Iga; Engels, Sylvain; Fesquet, Laurent (2019)

Skilled manpower shortage in microelectronics: a challenge for the French education microelectronics network. - Bonnaud, Olivier; Fesquet, Laurent; Bsiesy, Ahmad (2019)

A Distributed Body-Biasing Strategy for Asynchronous Circuits. - Fesquet, Laurent; Decoudu, Yoan; Jadue, Alexis Rodrigo Iga; Leite, Thiago Ferreira de Paiva; Rolloff, Otto Aureliano; Diallo, M.; Bastos, Rodrigo Possamai; Morin-Allory, Katell; Engels, Sylvain (2019)

A Digital Event-Based Strategy for ASK demodulation. - Jadue, Alexis Rodrigo Iga; Engels, Sylvain; Fesquet, Laurent (2019)

Architectures of bulk built-in current sensors for detection of transient faults in integrated circuits. - Bastos, Rodrigo Possamai; Guimaraes, Leonel Acunha; Torres, Frank Sill; Fesquet, Laurent (Microelectron. J., 2018)

A body built-in cell for detecting transient faults and dynamically biasing subcircuits of integrated systems. - Leite, Thiago Ferreira de Paiva; Fesquet, Laurent; Bastos, Rodrigo Possamai (Microelectron. Reliab., 2018)

A Cognitive Stochastic Machine Based on Bayesian Inference: A Behavioral Analysis. - Frisch, Raphael; Faix, Marvin; Mazer, Emmanuel; Fesquet, Laurent; Lux, Augustin (2018)

A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits. - Germain, Sophie; Engels, Sylvain; Fesquet, Laurent (2018)

Static Timing Analysis of Asynchronous Bundled-Data Circuits. - Gimenez, Gregoire; Cherkaoui, Abdelkarim; Cogniard, Guillaume; Fesquet, Laurent (2018)

Subthreshold logic for low-area and energy efficient true random number generator. - Coustans, Mathieu; Cherkaoui, Abdelkarim; Fesquet, Laurent; Terrier, Christian; Salgado, Stephanie; Eberhardt, Thomas; Kayal, Maher (2018)

Non-intrusive testing technique for detection of Trojans in asynchronous circuits. - Guimaraes, Leonel Acunha; Leite, Thiago Ferreira de Paiva; Bastos, Rodrigo Possamai; Fesquet, Laurent (2018)

Low Phase-Noise CMOS Quadrature Oscillator based on (N × 4)-stage Self-Timed Ring. - Elissati, Oussama; El-Hadbi, Assia; Cherkaoui, Abdelkarim; Rieubon, Sébastien; Fesquet, Laurent (2018)

An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting Systems. - Turko, Timothe; Uhring, Wilfried; Dadouche, Foudil; Fesquet, Laurent (2018)

Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems. - Jadue, Alexis Rodrigo Iga; Bastos, Rodrigo Possamai; Leite, Thiago Ferreira de Paiva; Rolloff, Otto Aureliano; Diallo, M.; Fesquet, Laurent (2018)

Strategy for higher education in electronic circuits and systems in the perspective of the up-coming digital society. - Bonnaud, Olivier; Fesquet, Laurent; Hébrard, Luc (2018)

A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines. - Simatic, Jean; Cherkaoui, Abdelkarim; Bertrand, François; Bastos, Rodrigo Possamai; Fesquet, Laurent (2017)

Event-driven image sensor application: Event-driven image segmentation. - Darwish, Amani; Abbass, Hassan; Fesquet, Laurent; Sicard, Gilles (2017)

Event-based design strategy for circuit electromagnetic compatibility. - Germain, Sophie; Engels, Sylvain; Fesquet, Laurent (2017)

High-level synthesis of an event-driven windowing process. - Qaisar, Saeed Mian; Simatic, Jean; Fesquet, Laurent (2017)

Towards consistency checking between HDL and UPF descriptions. - Kalsing, Arthur; Fesquet, Laurent; Aktouf, Chouki (2017)

A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions. - Kalsing, Arthur; Fesquet, Laurent; Aktouf, Chouki (2017)

CAR: On the highway towards de-synchronization. - Bertrand, François; Cherkaoui, Abdelkarim; Simatic, Jean; Maure, Anthony; Fesquet, Laurent (2017)

A Bayesian Stochastic Machine for Sound Source Localization. - Frisch, Raphael; Laurent, Raphaël; Faix, Marvin; Girin, Laurent; Fesquet, Laurent; Lux, Augustin; Droulez, Jacques; Bessière, Pierre; Mazer, Emmanuel (2017)

Seeking low-power synchronous/asynchronous systems: A FIR implementation case study. - Skaf, Ali; Simatic, Jean; Fesquet, Laurent (2017)

Detection of Layout-Level Trojans by Monitoring Substrate with Preexisting Built-in Sensors. - Guimaraes, Leonel Acunha; Bastos, Rodrigo Possamai; Fesquet, Laurent (2017)

Self-timed Ring based True Random Number Generator: Threat model and countermeasures. - Gimenez, Gregoire; Cherkaoui, Abdelkarim; Frisch, Raphael; Fesquet, Laurent (2017)

Innovative practice in the French microelectronics education targeting the industrial needs. - Bonnaud, Olivier; Fesquet, Laurent (2017)

On-the-fly and sub-gate-delay resolution TDC based on self-timed ring: A proof of concept. - El-Hadbi, Assia; Cherkaoui, Abdelkarim; Elissati, Oussama; Simatic, Jean; Fesquet, Laurent (2017)

Simple tri-state logic Trojans able to upset properties of ring oscillators. - Guimaraes, Leonel Acunha; Bastos, Rodrigo Possamai; Leite, Thiago Ferreira de Paiva; Fesquet, Laurent (2016)

Asynchronous implementation of an event-driven adaptive FIR filter. - Beyrouthy, Taha; Roshdy, Ahmed; Salman, Mohammad; Qaisar, Saeed Mian; Fesquet, Laurent (2016)

Levels, peaks, slopes... which sampling for which purpose? - Bidégaray-Fesquet, Brigitte; Fesquet, Laurent (2016)

High-level synthesis for event-based systems. - Simatic, Jean; Bastos, Rodrigo Possamai; Fesquet, Laurent (2016)

Delay partitioning helps reducing variability in 3DVLSI. - Ayres, A.; Rozeau, Olivier; Borot, B.; Fesquet, Laurent; Vinet, Maud (2016)

Practice in microelectronics education as a mandatory supplement to the future digital-based pedagogy: Strategy of the French national network. - Bonnaud, Olivier; Fesquet, Laurent (2016)

MOOC and practices in electrical and information engineering: Complementary approaches. - Bonnaud, Olivier; Fesquet, Laurent (2016)

Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuits. - Leite, Thiago Ferreira de Paiva; Bastos, Rodrigo Possamai; Jadue, Rodrigo Iga; Fesquet, Laurent (2016)

New asynchronous protocols for enhancing area and throughput in bundled-data pipelines. - Simatic, Jean; Cherkaoui, Abdelkarim; Bastos, Rodrigo Possamai; Fesquet, Laurent (2016)

Exploiting reliable features of asynchronous circuits for designing low-voltage components in FD-SOI technology. - Rolloff, Otto Aureliano; Bastos, Rodrigo Possamai; Fesquet, Laurent (Microelectron. Reliab., 2015)

A method to automatically determine the level-crossing thresholds in non-uniform sampling and processing. - Arslan, Cansu; Poujaud, Julien; Fesquet, Laurent (2015)

Data sampling and processing: Uniform vs. non-uniform schemes. - Beyrouthy, Taha; Fesquet, Laurent; Rolland, Robin (2015)

RTL simulation of an asynchronous reading architecture for an event-driven image sensor. - Darwish, Amani; Fesquet, Laurent; Sicard, Gilles (2015)

Communicating and smart objects: Multidisciplinary topics for the innovative education in microelectronics and its applications. - Bonnaud, Olivier; Fesquet, Laurent (2015)

Towards multidisciplinarity for microelectronics education: A strategy of the French national network. - Bonnaud, Olivier; Fesquet, Laurent (2015)

A generic clock controller for low power systems: Experimentation on an AXI bus. - Khatib, Chadi Al; Aupetit, Claire; Chevalier, Cyril; Aktouf, Chouki; Sicard, Gilles; Fesquet, Laurent (2015)

Adaptive rate filtering a computationally efficient signal processing approach. - Qaisar, Saeed Mian; Fesquet, Laurent; Renaudin, Marc (Signal Process., 2014)

Low data rate architecture for smart image sensor. - Darwish, Amani; Sicard, Gilles; Fesquet, Laurent (2014)

Trends in nanoelectronic education from FDSOI and FinFET technologies to circuit design specifications. - Bonnaud, Olivier; Fesquet, Laurent (2014)

Distributed asynchronous controllers for clock management in low power systems. - Khatib, Chadi Al; Aupetit, Claire; Chagoya, Alejandro; Chevalier, Cyril; Sicard, Gilles; Fesquet, Laurent (2014)

FINMINA: A French national project to promote innovation in higher education in microelectronics and nanotechnologies. - Bonnaud, Olivier; Nouet, Pascal; Fesquet, Laurent; Mohammed-Brahim, Taieb (2014)

1-Level crossing sampling scheme for low data rate image sensors. - Darwish, Amani; Fesquet, Laurent; Sicard, Gilles (2014)

Self-timed rings as low-phase noise programmable oscillators. - Fesquet, Laurent; Cherkaoui, Abdelkarim; Elissati, Oussama (2014)

Designing ultra-low power systems with non-uniform sampling and event-driven logic. - Roa, Giuseppe; Pelleter, Tugdual Le; Bonvilain, Agnès; Chagoya, Alejandro; Fesquet, Laurent (2014)

An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications. - Beyrouthy, Taha; Fesquet, Laurent (Int. J. Reconfigurable Comput., 2013)

Empirical Recovery of Input Nonlinearity in Distributed Element Models. - Sliwinski, Przemyslaw; Berezowski, Krzysztof S.; Wachel, Pawel; Sicard, Gilles; Fesquet, Laurent (2013)

Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation. - Yahya, Eslam; Fesquet, Laurent; Ismail, Yehea I.; Renaudin, Marc (2013)

A Self-Timed Ring Based True Random Number Generator. - Cherkaoui, Abdelkarim; Fischer, Viktor; Aubert, Alain; Fesquet, Laurent (2013)

A Very High Speed True Random Number Generator with Entropy Assessment. - Cherkaoui, Abdelkarim; Fischer, Viktor; Fesquet, Laurent; Aubert, Alain (2013)

Innovating projects as a pedagogical strategy for the French network for education in microélectronics and nanotechnologies. - Bonnaud, Olivier; Fesquet, Laurent (2013)

Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. - Cherkaoui, Abdelkarim; Fischer, Viktor; Aubert, Alain; Fesquet, Laurent (2012)

New pedagogical experiment leading to awareness in nanosciences and nanotechnologies for young generations at secondary school. - Excoffon, Evelyne; Papillon, Francine; Fesquet, Laurent; Bsiesy, Ahmad; Bonnaud, Olivier (2012)

Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs. - Zakaria, Hatem; Fesquet, Laurent (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Formal Verification of C-element Circuits. - Yan, Chao; Ouchet, Florent; Fesquet, Laurent; Morin-Allory, Katell (2011)

Does asynchronous technology bring robustness in synchronous circuit monitoring? - Porcher, Alexandre; Morin-Allory, Katell; Fesquet, Laurent; Chagoya, Alejandro (2011)

C-elements for Hardened Self-timed Circuits. - Ouchet, Florent; Morin-Allory, Katell; Fesquet, Laurent (2011)

An event-driven FIR filter: Design and implementation. - Beyrouthy, Taha; Fesquet, Laurent (2011)

A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback - Chaudhuri, Sumanta; Guilley, Sylvain; Hoogvorst, Philippe; Danger, Jean-Luc; Beyrouthy, Taha; Razafindraibe, Alin; Fesquet, Laurent; Renaudin, Marc (CoRR, 2011)

IIR digital filtering of non-uniformly sampled signals via state representation. - Fesquet, Laurent; Bidégaray-Fesquet, Brigitte (Signal Process., 2010)

Delay Insensitivity Does Not Mean Slope Insensitivity! - Ouchet, Florent; Morin-Allory, Katell; Fesquet, Laurent (2010)

Synthesis of asynchronous monitors for critical electronic systems. - Porcher, Alexandre; Morin-Allory, Katell; Fesquet, Laurent (2010)

Targeting ultra-low power consumption with non-uniform sampling and filtering. - Fesquet, Laurent; Sicard, Gilles; Bidégaray-Fesquet, Brigitte (2010)

Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case. - Elissati, Oussama; Yahya, Eslam; Rieubon, Sébastien; Fesquet, Laurent (2010)

Self-Timed Rings: A Promising Solution for Generating High-Speed High-Resolution Low-Phase Noise Clocks. - Elissati, Oussama; Rieubon, Sébastien; Yahya, Eslam; Fesquet, Laurent (2010)

A high-speed high-resolution low-phase noise oscillator using self-timed rings. - Elissati, Oussama; Yahya, Eslam; Rieubon, Sébastien; Fesquet, Laurent (2010)

Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling. - Qaisar, Saeed Mian; Fesquet, Laurent; Renaudin, Marc (EURASIP J. Adv. Signal Process., 2009)

Constrained Asynchronous Ring Structures for Robust Digital Oscillators. - Hamon, Jérémie; Fesquet, Laurent; Miscopein, Benoit; Renaudin, Marc (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Controlling energy and process variability in System-on-Chips: needs for control theory. - Fesquet, Laurent; Zakaria, Hatem (2009)

Programmable/Stoppable Oscillator Based on Self-Timed Rings. - Yahya, Eslam; Elissati, Oussama; Zakaria, Hatem; Fesquet, Laurent; Renaudin, Marc (2009)

RAT-based formal verification of QDI asynchronous controllers. - Alsayeg, Khaled; Morin-Allory, Katell; Fesquet, Laurent (2009)

Asynchronous design: A promising paradigm for electronic circuits and systems. - Yahya, Eslam; Fesquet, Laurent (2009)

Updates on the potential of clock-less logics to strengthen cryptographic circuits against side-channel attacks. - Guilley, Sylvain; Chaudhuri, Sumanta; Sauvage, Laurent; Danger, Jean-Luc; Beyrouthy, Taha; Fesquet, Laurent (2009)

An Adaptive Resolution Computationally Efficient Short-Time Fourier Transform. - Qaisar, Saeed Mian; Fesquet, Laurent; Renaudin, Marc (J. Electr. Comput. Eng., 2008)

Physical Design of FPGA Interconnect to Prevent Information Leakage. - Chaudhuri, Sumanta; Guilley, Sylvain; Hoogvorst, Philippe; Danger, Jean-Luc; Beyrouthy, Taha; Razafindraibe, Alin; Fesquet, Laurent; Renaudin, Marc (2008)

High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators. - Hamon, Jérémie; Fesquet, Laurent; Miscopein, Benoit; Renaudin, Marc (2008)

A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks - Hoogvorst, Philippe; Guilley, Sylvain; Chaudhuri, Sumanta; Danger, Jean-Luc; Beyrouthy, Taha; Fesquet, Laurent (CoRR, 2008)

Computationally efficient adaptive rate sampling and filtering. - Qaisar, Saeed Mian; Fesquet, Laurent; Renaudin, Marc (2007)

Asynchronous online-monitoring of logical and temporal assertions. - Morin-Allory, Katell; Fesquet, Laurent; Roustan, Benjamin; Borrione, Dominique (2007)

A Novel Asynchronous e-FPGA Architecture for Security Applications. - Beyrouthy, Taha; Razafindraibe, Alin; Fesquet, Laurent; Renaudin, Marc; Chaudhuri, Sumanta; Guilley, Sylvain; Danger, Jean-Luc; Hoogvorst, Philippe (2007)

Adaptive Rate Filtering Fora Signal Driven Sampling Scheme. - Qaisar, Saeed Mian; Fesquet, Laurent; Renaudin, Marc (2007)

A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. - Hoogvorst, Philippe; Guilley, Sylvain; Chaudhuri, Sumanta; Razafindraibe, Alin; Beyrouthy, Taha; Fesquet, Laurent (2007)

FPGA Architecture for Multi-Style Asynchronous Logic - Huot, N.; Dubreuil, H.; Fesquet, Laurent; Renaudin, Marc (CoRR, 2007)

Spectral analysis of a signal driven sampling scheme. - Qaisar, Saeed Mian; Fesquet, Laurent; Renaudin, Marc (2006)

Asynchronous Assertion Monitors for multi-Clock Domain System Verification. - Morin-Allory, Katell; Fesquet, Laurent; Borrione, Dominique (2006)

State-holding in Look-Up Tables: application to asynchronous logic. - Fesquet, Laurent; Folco, Bertrand; Steiner, Mathieu; Renaudin, Marc (2006)

FPGA Architecture for Multi-Style Asynchronous Logic. - Huot, N.; Dubreuil, H.; Fesquet, Laurent; Renaudin, Marc (2005)

PSL-based online monitoring of digital systems. - Borionne, D.; Liu, M.; Ostier, P.; Fesquet, Laurent (2005)

A Programmable Logic Architecture for Prototyping Clockless Circuits. - Fesquet, Laurent; Renaudin, Marc (2005)

GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. - Quartana, Jerome; Renane, Salim; Baixas, Arnaud; Fesquet, Laurent; Renaudin, Marc (2005)

Asynchronous Systems on Programmable Logic. - Fesquet, Laurent; Quartana, Jerome; Renaudin, Marc (2005)

Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. - Folco, Bertrand; Brégier, Vivian; Fesquet, Laurent; Renaudin, Marc (2005)

Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. - Quartana, Jerome; Fesquet, Laurent; Renaudin, Marc (2005)

Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005 (IEEE, 2005)

La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués. - Fesquet, Laurent; Salhiene, Mohammed Es; Renaudin, Marc (Ann. des Télécommunications, 2004)

Asynchronous FIR Filters: Towards a New Digital Processing Chain. - Aeschlimann, F.; Allier, Emmanuel; Fesquet, Laurent; Renaudin, Marc (2004)

A New Class of Asynchronous A/D Converters Based on Time Quantization. - Allier, Emmanuel; Sicard, Gilles; Fesquet, Laurent; Renaudin, Marc (2003)

High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems. - Rigaud, Jean-Baptiste; Fesquet, Laurent; Renaudin, Marc; Quartana, Jerome (2002)

Implementing Asynchronous Circuits on LUT Based FPGAs. - Ho, Quoc Thai; Rigaud, Jean-Baptiste; Fesquet, Laurent; Renaudin, Marc; Rolland, Robin (2002)

Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. - Duc, Anh Vu Dihn; Fesquet, Laurent; Renaudin, Marc (2002)

Low-Power Asynchronous A/D Conversion. - Allier, Emmanuel; Fesquet, Laurent; Renaudin, Marc; Sicard, Gilles (2002)

Dynamic Voltage Scheduling for Real Time Asynchronous Systems. - Salhiene, Mohammed Es; Fesquet, Laurent; Renaudin, Marc (2002)

Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems. - Rigaud, Jean-Baptiste; Quartana, Jerome; Fesquet, Laurent; Renaudin, Marc (2001)

Implementing Snoop-Coherence Protocol for Future SMP Architectures. - Hlayhel, Wissam; Collet, Jacques Henri; Fesquet, Laurent (1999)

Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures. - Hlayhel, Wissam; Litaize, Daniel; Fesquet, Laurent; Collet, Jacques Henri (1998)