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2020 – today
- 2023
[c43]Shih-Jung Pao, Chuan-Pin Huang, Yen-Chi Peng, Ing-Jer Huang:
Focusing on the Key Suspicious Trojan Nets with a Collaborative Approach. ISQED 2023: 1-8- 2022
- [c42]Ing-Jer Huang, Yi-Ju Ke, Shih-Jung Pao:
Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors. MCSoC 2022: 284-290 - 2021
- [j23]Wen-Lan Wu
, Jing-Min Liang, Chien-Fei Chen, Kuei-Lan Tsai, Nian-Shing Chen, Kuo-Chin Lin, Ing-Jer Huang:
Creating a Scoring System with an Armband Wearable Device for Table Tennis Forehand Loop Training: Combined Use of the Principal Component Analysis and Artificial Neural Network. Sensors 21(11): 3870 (2021)
2010 – 2019
- 2019
- [c41]Hsu-Kang Dow, Ing-Jer Huang, Robert Rieger, Ko-Chi Kuo, Lan-Yuen Guo, Shih-Jung Pao:
A Bio-Sensing System-on-Chip and Software for Smart Clothes. ICCE 2019: 1-4 - 2018
- [j22]Ing-Jer Huang, Chun-Hung Lai, Yun-Chung Yang, Hsu-Kang Dow, Hung-Lun Chen:
A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory. IEEE Trans. Very Large Scale Integr. Syst. 26(4): 663-670 (2018) - 2016
- [c40]Tsun-Hsin Chang, Shao-Chieh Hou, Ing-Jer Huang:
A unified GDB-based source-transaction level SW/HW co-debugging. APCCAS 2016: 506-509 - [c39]Jyun-Yan Li, Ing-Jer Huang:
Full system verification of compatible microprocessors with a dual physical core verification platform. ISOCC 2016: 357-358 - 2015
- [c38]Hsu-Kang Dow, Ching-Hua Huang, Chun-Hung Lai, Kai-Hsiang Tsao, Sheng-Chih Tseng, Kun-Yi Wu, Ting-Hsuan Wu, Ho-Chun Yang, Da-Jing Zhang-Jian, Yun-Nan Chang, Steve Haga, Shen-Fu Hsiao, Ing-Jer Huang, Shiann-Rong Kuang, Chung-Nan Lee:
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. VLSI-DAT 2015: 1-4 - 2014
- [j21]Chun-Hung Lai, Yun-Chung Yang, Ing-Jer Huang:
A Versatile Data Cache for Trace Buffer Support. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(11): 3145-3154 (2014) - [c37]Ping-Chun Lee, Ing-Jer Huang:
Reconfigurable Bus Monitor Tool Suite for on-chip SoC for performance and protocol monitoring. ReCoSoC 2014: 1-6 - 2013
- [c36]Chun-Hung Lai, Yun-Chung Yang, Ing-Jer Huang:
A versatile data cache for trace buffer support. VLSI-DAT 2013: 1-4 - 2012
- [c35]Yi-Hao Chang, Chi-Tsai Yeh, Ing-Jer Huang, Shau-Yin Tseng:
A performance monitoring tool suite for 3D graphics SoC application. APCCAS 2012: 444-447 - [c34]Cheng-Ta Wu, Feng-Xiang Huang, Kuan-Fu Kuo, Ing-Jer Huang:
An OCP-AHB bus wrapper with built-in ICE support for SOC integration. VLSI-DAT 2012: 1-4 - 2011
- [j20]Chi-Tsai Yeh, Chun-Hao Wang, Ing-Jer Huang, Weng-Fai Wong:
Internet-based hardware/software co-design framework for embedded 3D graphics applications. EURASIP J. Adv. Signal Process. 2011: 25 (2011) - [j19]Liang-Bi Chen, Yen-Ling Chen, Ing-Jer Huang:
A Real-Time Power Analysis Platform for Power-Aware Embedded System Development. J. Inf. Sci. Eng. 27(3): 1165-1182 (2011) - [j18]Chun-Hung Lai, Fu-Ching Yang, Ing-Jer Huang:
A Trace-Capable Instruction Cache for Cost-Efficient Real-Time Program Trace Compression in SoC. IEEE Trans. Computers 60(12): 1665-1677 (2011) - [j17]Fu-Ching Yang, Yi-Ting Lin, Chung-Fu Kao, Ing-Jer Huang:
An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC. IEEE Trans. Very Large Scale Integr. Syst. 19(4): 571-584 (2011) - 2010
- [j16]Liang-Bi Chen, Jiun-Cheng Ju, Chien-Chou Wang, Ing-Jer Huang:
HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms. IEICE Trans. Inf. Syst. 93-D(8): 2100-2108 (2010) - [j15]Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang:
A Reverse-Encoding-Based On-Chip Bus Tracer for Efficient Circular-Buffer Utilization. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 732-741 (2010) - [c33]Liang-Bi Chen, Tsung-Yu Ho, Jiun-Cheng Ju, Cheng-Lung Chiang, Chung-Nan Lee, Ing-Jer Huang:
An embedded debugging/performance monitoring engine for a tile-based 3D graphics SoC development. ASP-DAC 2010: 353-354
2000 – 2009
- 2009
- [j14]Liang-Bi Chen, Chi-Tsai Yeh, Hung-Yu Chen, Ing-Jer Huang:
A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 3193-3202 (2009) - [c32]Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang:
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. ASP-DAC 2009: 131-132 - [c31]Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang:
A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization. ASP-DAC 2009: 721-726 - [c30]Chun-Hung Lai, Fu-Ching Yang, Chung-Fu Kao, Ing-Jer Huang:
A trace-capable instruction cache for cost efficient real-time program trace compression in SoC. DAC 2009: 136-141 - [c29]Fu-Ching Yang, Cheng-Lung Chiang, Ing-Jer Huang:
A Reverse-encoding-based On-chip AHB Bus Tracer Supporting both Post-T and Pre-T Trace. ISCAS 2009: 788 - 2008
- [j13]Chung-Fu Kao, Hsin-Ming Chen, Ing-Jer Huang:
Hardware-Software Approaches to In-Circuit Emulation for Embedded Processors. IEEE Des. Test Comput. 25(5): 462-477 (2008) - [j12]Fu-Ching Yang, Wen-Kai Huang, Jing-Kun Zhong, Ing-Jer Huang:
Automatic Verification of External Interrupt Behaviors for Microprocessor Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1670-1683 (2008) - [c28]Chung-Ping Young, Chung-Chu Chia, Liang-Bi Chen, Ing-Jer Huang:
On-Chip-Network cryptosystem: A high throughput and high security architecture. APCCAS 2008: 1276-1279 - [c27]Liang-Bi Chen, Yung-Chih Liu, Chen-Hung Chen, Chung-Fu Kao, Ing-Jer Huang:
Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor. ASP-DAC 2008: 117-118 - [c26]Yi-Ting Lin, Wen-Chi Shiue, Ing-Jer Huang:
A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer. DAC 2008: 862-865 - [c25]Fu-Ching Yang, Jing-Kun Zhong, Ing-Jer Huang:
Verifying external interrupts of embedded microprocessor in SoC with on-chip bus. ICCAD 2008: 372-377 - [c24]Chung-Ping Young, Chung-Chu Chia, Liang-Bi Chen, Ing-Jer Huang:
NCPA: A Scheduling Algorithm for Multi-cipher and Multi-mode Reconfigurable Cryptosystem. IIH-MSP 2008: 1356-1359 - [c23]Yi-Ting Lin, Chien-Chou Wang, Ing-Jer Huang:
AMBA AHB bus potocol checker with efficient debugging mechanism. ISCAS 2008: 928-931 - 2007
- [j11]Chung-Fu Kao, Shyh-Ming Huang, Ing-Jer Huang:
A Hardware Approach to Real-Time Program Trace Compression for Embedded Processors. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(3): 530-543 (2007) - [c22]Chung-Fu Kao, Chi-Hung Lin, Ing-Jer Huang:
Configurable AMBA On-Chip Real-Time Signal Tracer. ASP-DAC 2007: 114-115 - [c21]Fu-Ching Yang, Ing-Jer Huang:
An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools. ASP-DAC 2007: 902-907 - [c20]Chung-Fu Kao, Ing-Jer Huang, Chi-Hung Lin:
An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration. DAC 2007: 477-482 - [c19]Fu-Ching Yang, Wen-Kai Huang, Ing-Jer Huang:
Automatic Verification of External Interrupt Behaviors for Microprocessor Design. DAC 2007: 896-901 - [c18]Tse-Chen Yeh, Tsung-Yu Ho, Hung-Yu Chen, Ing-Jer Huang:
SystemC-Based Design Space Exploration of a 3D Graphics Acceleration SoC for Consumer Electronics. EUC 2007: 531-540 - [c17]Liang-Bi Chen, Ching-Chi Hu, Yen-Ling Chen, Chi-Wei Chu, Ing-Jer Huang:
The AES Design Space Exploration with a Soft IP Generator. IIH-MSP 2007: 385-388 - 2006
- [c16]Liang-Bi Chen, Ing-Jer Huang, Yuan-Long Jeang:
Design of a Dynamic PCM Selector for Non-deterministic Environment. APCCAS 2006: 1124-1127 - 2005
- [c15]Wen-Kai Huang, I-Ting Lin, Shi-Wei Chen, Ing-Jer Huang:
A cost-effective media processor for embedded applications [audio decoder example]. ISCAS (6) 2005: 6122-6125 - 2003
- [j10]Ing-Jer Huang, Dao-Zhen Chen:
Automatic Assembly Program Retargeting for Micrco controllers. J. Inf. Sci. Eng. 19(5): 717-743 (2003) - [j9]Ing-Jer Huang, Dao-Zhen Chen:
Mining Correlations of Human Gene Expression from Digital Gene Expression Profiles. J. Inf. Sci. Eng. 19(6): 909-921 (2003) - [c14]Shyh-Ming Huang, Ing-Jer Huang, Chung-Fu Kao:
Reconfigurable real-time address trace compressor for embedded microprocessors. FPT 2003: 196-203 - 2002
- [j8]Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching-Nan Juan, Tai-An Lu:
A Retargetable Embedded In-Circuit Emulation Module for Microprocessors. IEEE Des. Test Comput. 19(4): 28-38 (2002) - [j7]Ing-Jer Huang, Li-Rong Wang, Yu-Min Wang, Tai-An Lu:
Design Exploration of an Industrial Embedded Microcontroller: Performance, Cost and Software Compatibility. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2624-2635 (2002) - [j6]Ing-Jer Huang, Ping-Huei Xie:
Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors. IEEE Trans. Very Large Scale Integr. Syst. 10(1): 44-54 (2002) - 2001
- [j5]Ing-Jer Huang:
Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors. ACM Trans. Design Autom. Electr. Syst. 6(1): 93-121 (2001) - [c13]Ming-Chih Chen, Ing-Jer Huang, Chung-Ho Chen:
Parameterized MAC unit implementation. ASP-DAC 2001: 23-24 - [c12]Ing-Jer Huang, Hsin-Ming Chen, Chung-Fu Kao:
Reusable embedded in-circuit emulator. ASP-DAC 2001: 33-34 - 2000
- [j4]Ing-Jer Huang, Wen-Fu Kao:
A Machine State Transition Approach to Instruction Retargeting for Embedded Microprocessors. Des. Autom. Embed. Syst. 5(2): 153-177 (2000) - [c11]Ing-Jer Huang, Dao-Zhen Chen:
A new approach to assembly software retargeting for microcontrollers. ASP-DAC 2000: 229-234
1990 – 1999
- 1999
- [j3]Ing-Jer Huang, Li-Rong Wang:
Automatic Simulation and Verification of Pipelined Microcontrollers. J. Inf. Sci. Eng. 15(2): 307-320 (1999) - [c10]Ing-Jer Huang, Tai-An Lu:
ICEBERG: An Embedded In-Circuit Emulator Synthesizer for Microcontrollers. DAC 1999: 580-585 - 1998
- [j2]Ing-Jer Huang:
A Case Study: Synthesis and Exploration of Instruction Set Design for Application-Specific Symbolic Computing. J. Inf. Sci. Eng. 14(4): 821-842 (1998) - [c9]Ing-Jer Huang, Tzu-Chin Peng:
Analysis of ×86 instruction set usage for DOS/Windows applications and its implication on superscalar design. ICCD 1998: 566-573 - [c8]Ing-Jer Huang, Ping-Huei Xie:
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation. ISSS 1998: 131-136 - 1997
- [c7]Ing-Jer Huang, Li-Rong Wang, Yu-Min Wang:
Synthesis and analysis of an industrial embedded microcontroller. ASP-DAC 1997: 151-156 - 1995
- [j1]Ing-Jer Huang, Alvin M. Despain:
Synthesis of application specific instruction sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 663-675 (1995) - 1994
- [c6]Ing-Jer Huang, Alvin M. Despain:
Synthesis of Instruction Sets for Pipelined Microprocessors. DAC 1994: 5-11 - [c5]Ing-Jer Huang, Alvin M. Despain:
Generating instruction sets and microarchitectures from applications. ICCAD 1994: 391-396 - 1993
- [c4]Ing-Jer Huang, Alvin M. Despain:
Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors. ICCAD 1993: 594-599 - [c3]Ing-Jer Huang, Alvin M. Despain:
An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processors. MICRO 1993: 236-246 - 1992
- [c2]Ing-Jer Huang, Alvin M. Despain:
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers. DAC 1992: 135-140 - [c1]Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain:
Application-Driven Design Automation for Microprocessor Design. DAC 1992: 512-517
Coauthor Index
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