Fabrication of Hybrid Fin/Planar LDMOS with Modulation Gate. - Chen, Zih-Fei; Huang, Ya-Chi; Lai, Yu-Shen; Wu, Yi-Ting; Huang, Cheng-Ming; Chiang, Meng-Hsueh (2024)

MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization. - Lin, W.-C.; Huang, H.-P.; Kao, Kuo-Hsing; Chiang, Meng-Hsueh; Lu, Darsen D.; Hsu, Wei-Chou; Wang, Yeong-Her; Ma, William Cheng-Yu; Tsai, Hann-Huei; Lee, Y.-J.; Chiang, H.-L.; Wang, J.-F.; et al. (2023)

Performance Comparison of SRAM Designs Implemented with Silicon-On-Insulator Nanosheet Transistors and Bulk FinFETs. - Chen, Po-Chih; Wu, Yi-Ting; Chiang, Meng-Hsueh (2023)

How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology. - Chiang, H.-L.; Hadi, Richard A.; Wang, J.-F.; Han, Hung-Chi; Wu, J.-J.; Hsieh, H.-H.; Horng, J.-J.; Chou, W.-S.; Lien, B.-S.; Chang, C.-H.; Chen, Y.-C.; Wang, Yeong-Her; et al. (2023)

Back-Bias Modulated UTBB SOI for System-on-Chip I/O Cells. - Chang, Ming-Yu; Chao, Po-Yu; Chiang, Meng-Hsueh (2021)

Compact Device Models for FinFET and Beyond. - Lu, Darsen D.; Dunga, Mohan V.; Niknejad, Ali M.; Hu, Chenming; Liang, Fu-Xiang; Hung, Wei-Chen; Lee, Jia-Wei; Hsu, Chun-Hsiang; Chiang, Meng-Hsueh (CoRR, 2020)

Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications. - Huang, Ya-Chi; Chiang, Meng-Hsueh; Wang, Shui-Jinn (2019)

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires. - Huang, Ya-Chi; Chiang, Meng-Hsueh; Wang, Shui-Jinn; Gupta, Sumeet Kumar (2018)

Body-biasing assisted vmin optimization for 5nm-node multi-Vt FD-SOI 6T-SRAM. - Chen, Jheng-Yi; Chang, Ming-Yu; Chen, Shi-Hao; Lee, Jia-Wei; Chiang, Meng-Hsueh (2018)

Threshold-voltage variability analysis and modeling for junctionless double-gate transistors. - Chen, Chun-Yu; Lin, Jyi-Tsong; Chiang, Meng-Hsueh (Microelectron. Reliab., 2017)

Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes. - Wu, Meng-Yen; Chiang, Meng-Hsueh (2016)

6-T SRAM performance assessment with stacked silicon nanowire MOSFETs. - Huang, Ya-Chi; Chiang, Meng-Hsueh; Hsu, Wei-Chou; Cheng, Shiou-Ying (2015)

Assessment of structure variation in silicon nanowire FETs and impact on SRAM. - Liao, Yi-Bo; Chiang, Meng-Hsueh; Kim, Keunwoo; Hsu, Wei-Chou (Microelectron. J., 2012)

Design issues and insights of multi-fin bulk silicon FinFETs. - Li, Hsun; Chiang, Meng-Hsueh (2012)

Low power design of phase-change memory based on a comprehensive model. - Chiang, Meng-Hsueh; Liao, Yi-Bo; Lin, Jun-Tin; Hsu, Wei-Chou; Yu, Chu; Chiang, Pei-Chia; Hsu, Y.-Y.; Liu, W.-H.; Sheu, Shyh-Shyuan; Su, Keng-Li; Kao, Ming-Jer; Tsai, Ming-Jinn (IET Comput. Digit. Tech., 2010)