Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. - Ye, Lun; Chang, Foong-Charn; Feldmann, Peter; Chadha, Rakesh; Ns, Nagaraj; Cano, Frank (1999)

M3-a multilevel mixed-mode mixed A/D simulator. - Chadha, Rakesh; Visweswariah, Chandramouli; Chen, Chin-Fu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Switched-capacitor simulation models for full-chips verification. - Chanak, Tom; Chadha, Rakesh; Singhal, Kishore (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Model Development and Verification for High Level Analog Blocks. - Visweswariah, Chandramouli; Chadha, Rakesh; Chen, Chin-Fu (1988)

M3-a multilevel mixed-mode mixed D/A simulator. - Chadha, Rakesh; Chen, Chin-Fu (1988)

Extension of a transistor level digital timing simulator to include first order analog behavior. - Chadha, Rakesh; Chen, Chin-Fu (1988)

WATOPT -- An Optimizer for Circuit Applications. - Chadha, Rakesh; Singhal, Kishore; Vlach, Jirí; Christen, Ernst; Vlach, Milan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)