High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm. - Wen, Wanting; Zhao, Guangchao; Hu, Wanbo; Li, Ziye; Wang, Xingli; Friedman, Eby G.; Tay, Beng Kang; Ke, Shaolin; Huang, Mingqiang (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Network-on-Interposer Co-Design for Heterogeneous Chiplet-Based Integrated Systems. - Ayes, Andres; Friedman, Eby G.; Wolf, Marilyn (2025)

Partitioning SFQ Circuits for Serial Biasing in Heterogeneous Circuits. - Oluwadamilare, Tejumadejesu; Friedman, Eby G. (2025)

Test Modules for Enhanced Testability of Single Flux Quantum Integrated Circuits. - Qoutb, Abdelrahman G.; Kawa, Jamil; Friedman, Eby G. (J. Electron. Test., 2024)

Harnessing stochasticity for superconductive multi-layer spike-rate-coded neuromorphic networks. - Edwards, Alexander J.; Krylov, Gleb; Friedman, Joseph S.; Friedman, Eby G. (Neuromorph. Comput. Eng., 2024)

Power Aware Placement of On-Chip Voltage Regulators. - Bairamkulov, Rassul; Friedman, Eby G. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms. - Zhao, Guangchao; Zeng, Zhiwei; Wang, Xingli; Qoutb, Abdelrahman G.; Coquet, Philippe; Friedman, Eby G.; Tay, Beng Kang; Huang, Mingqiang (IEEE Trans. Emerg. Top. Comput., 2024)

Thermal Exploration of RSFQ Integrated Circuits. - Mitrovic, Ana; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Quasi-Adiabatic Clock Networks in 3-D Voltage Stacked Systems. - Ayes, Andres; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces. - Ayes, Andres; Friedman, Eby G. (Integr., 2023)

Double magnetic tunnel junction two bit memory and nonvolatile logic for in situ computing. - Qoutb, Abdelrahman G.; Friedman, Eby G. (Microelectron. J., 2023)

Temperature-frequency boundary of cryogenic dynamic logic. - Zhuldassov, Nurzhan; Friedman, Eby G. (Microelectron. J., 2023)

Thermal Optimization of Hybrid Cryogenic Computing Systems. - Zhuldassov, Nurzhan; Bairamkulov, Rassul; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Dual Sawtooth-Based Delay Locked Loops for Heterogeneous 3-D Clock Networks. - Ayes, Andres; Friedman, Eby G. (2023)

Deep Neuromorphic Networks with Superconducting Single Flux Quanta. - Krylov, Gleb; Edwards, Alexander J.; Friedman, Joseph S.; Friedman, Eby G. (CoRR, 2023)

Inductive noise coupling in multilayer superconductive ICs. - Krylov, Gleb; Friedman, Eby G. (Microelectron. J., 2022)

SPROUT - Smart Power Routing Tool for Board-Level Exploration and Prototyping. - Bairamkulov, Rassul; Roy, Abinash; Nagarajan, Mahalingam; Srinivas, Vaishnav; Friedman, Eby G. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

QuCTS - Single-Flux Quantum Clock Tree Synthesis. - Bairamkulov, Rassul; Jabbari, Tahereh; Friedman, Eby G. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Superconductive Logic Using 2ϕ - Josephson Junctions With Half Flux Quantum Pulses. - Salameh, Issa; Friedman, Eby G.; Kvatinsky, Shahar (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Surface Inductance of Superconductive Striplines. - Jabbari, Tahereh; Friedman, Eby G. (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Double Magnetic Tunnel Junction-Based Nonvolatile Logic. - Qoutb, Abdelrahman G.; Friedman, Eby G. (2022)

Converter Topologies for On-Package Voltage Stacking. - Zhuldassov, Nurzhan; Xu, Kan; Friedman, Eby G. (2022)

SPROUT - Smart Power ROUting Tool for Board-Level Exploration and Prototyping. - Bairamkulov, Rassul; Roy, Abinash; Nagarajan, Mali; Srinivas, Vaishnav; Friedman, Eby G. (2021)

MTJ-Based Dithering for Stochastic Analog-to-Digital Conversion. - Mitrovic, Ana; Friedman, Eby G. (2021)

Inductive Noise Coupling in Superconductive Passive Transmission Lines. - Krylov, Gleb; Friedman, Eby G. (2021)

Power Delivery Exploration Methodology Based on Constrained Optimization. - Bairamkulov, Rassul; Xu, Kan; Popovich, Mikhail; Ochoa, Juan; Srinivas, Vaishnav; Friedman, Eby G. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Effective Resistance of Finite Two-Dimensional Grids Based on Infinity Mirror Technique. - Bairamkulov, Rassul; Friedman, Eby G. (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout Regulators. - Ciprut, Albert; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Distributed Spintronic/CMOS Sensor Network for Thermal-Aware Systems. - Qoutb, Abdelrahman G.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Design Methodology for Distributed Large-Scale ERSFQ Bias Networks. - Krylov, Gleb; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Graph-Based Power Network Routing for Board-Level High Performance Systems. - Bairamkulov, Rassul; Friedman, Eby G.; Roy, Abinash; Nagarajan, Mali; Srinivas, Vaishnav (2020)

Bias Distribution in ERSFQ VLSI Circuits. - Krylov, Gleb; Friedman, Eby G. (2020)

Spintronic/CMOS-Based Thermal Sensors. - Qoutb, Abdelrahman G.; Friedman, Eby G. (2020)

Multi-Bit CNT TSV for 3-D ICs. - Vaisband, Boris; Maurice, Ange; Tan, Chong Wei; Tay, Beng Kang; Friedman, Eby G. (2020)

Challenges in High Current On-Chip Voltage Stacked Systems. - Xu, Kan; Friedman, Eby G. (2020)

Distributed Port Assignment for Extraction of Power Delivery Networks. - Xu, Kan; Friedman, Eby G.; Popovich, Mikhail; Sizikov, Gregory (2020)

Cryogenic Dynamic Logic. - Zhuldassov, Nurzhan; Friedman, Eby G. (2020)

Global interconnects in VLSI complexity single flux quantum systems. - Jabbari, Tahereh; Friedman, Eby G. (2020)

Effective Resistance of Two-Dimensional Truncated Infinite Mesh Structures. - Bairamkulov, Rassul; Friedman, Eby G. (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators. - Ciprut, Albert; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

PMTJ Temperature Sensor Utilizing VCMA. - Qoutb, Abdelrahman G.; Friedman, Eby G. (2019)

Heterogeneous 3-D ICs as a platform for hybrid energy harvesting in IoT systems. - Vaisband, Boris; Friedman, Eby G. (Future Gener. Comput. Syst., 2018)

Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs. - Xu, Kan; Patel, Ravi; Raghavan, Praveen; Friedman, Eby G. (Integr., 2018)

Memristor-Based Circuit Design for Multilayer Neural Networks. - Zhang, Yang; Wang, Xiaoping; Friedman, Eby G. (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays With Selectors. - Ciprut, Albert; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2018)

MTJ Magnetization Switching Mechanisms for IoT Applications. - Qoutb, Abdelrahman G.; Friedman, Eby G. (2018)

Versatile Framework for Power Delivery Exploration. - Bairamkulov, Rassul; Xu, Kan; Friedman, Eby G.; Popovich, Mikhail; Ochoa, Juan; Srinivas, Vaishnav (2018)

Hybrid Write Bias Scheme for Non-Volatile Resistive Crossbar Arrays. - Ciprut, Albert; Friedman, Eby G. (2018)

Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor. - Krylov, Gleb; Friedman, Eby G. (2018)

On the write energy of non-volatile resistive crossbar arrays with selectors. - Ciprut, Albert; Friedman, Eby G. (2018)

Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies. - Shapiro, Alexander E.; Friedman, Eby G. (J. Low Power Electron., 2017)

Hexagonal TSV Bundle Topology for 3-D ICs. - Vaisband, Boris; Friedman, Eby G. (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Memristive Model for Synaptic Circuits. - Zhang, Yang; Wang, Xiaoping; Li, Yi; Friedman, Eby G. (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors. - Ciprut, Albert; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Test point insertion for RSFQ circuits. - Krylov, Gleb; Friedman, Eby G. (2017)

Hybrid energy harvesting in 3-D IC IoT devices. - Vaisband, Boris; Friedman, Eby G. (2017)

On the stability of distributed on-chip low dropout regulators. - Ciprut, Albert; Friedman, Eby G. (2017)

Adaptive power gating of 32-bit Kogge Stone adder. - Shapiro, Alexander E.; Atallah, Francois; Kim, Kyugseok; Jeong, Jihoon; Fischer, Jeff; Friedman, Eby G. (Integr., 2016)

Heterogeneous 3-D circuits: Integrating free-space optics with CMOS. - Savidis, Ioannis; Ciftcioglu, Berkehan; Xu, Jie; Hu, Jianyun; Jain, Manish; Berman, Rebecca; Xue, Jing; Liu, Peng; Moore, Duncan; Wicks, Gary; Huang, Michael C.; Wu, Hui; et al. (Microelectron. J., 2016)

Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing. - Patel, Ravi; Guo, Xiaochen; Guo, Qing; Ipek, Engin; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2016)

PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors. - Wang, Jinhui; Gong, Na; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits. - Shapiro, Alexander E.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS. - Bai, Yuxin; Song, Yanwei; Bojnordi, Mahdi Nazm; Shapiro, Alexander E.; Friedman, Eby G.; Ipek, Engin (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Noise Coupling Models in Heterogeneous 3-D ICs. - Vaisband, Boris; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs. - Patel, Ravi; Xu, Kan; Friedman, Eby G.; Raghavan, Praveen (2016)

Power noise in 14, 10, and 7 nm FinFET CMOS technologies. - Patel, Ravi; Friedman, Eby G.; Raghavan, Praveen (2016)

Design models of resistive crossbar arrays with selector devices. - Ciprut, Albert; Friedman, Eby G. (2016)

Layer ordering to minimize TSVs in heterogeneous 3-D ICs. - Vaisband, Boris; Friedman, Eby G. (2016)

Energy efficient adaptive clustering of on-chip power delivery systems. - Vaisband, Inna; Friedman, Eby G. (Integr., 2015)

Scaling trends of power noise in 3-D ICs. - Xu, Kan; Friedman, Eby G. (Integr., 2015)

Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing. - Guo, Qing; Guo, Xiaochen; Bai, Yuxin; Patel, Ravi; Ipek, Engin; Friedman, Eby G. (IEEE Micro, 2015)

VTEAM: A General Model for Voltage-Controlled Memristors. - Kvatinsky, Shahar; Ramadan, Misbah; Friedman, Eby G.; Kolodny, Avinoam (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Energy-Efficient Nonvolatile Flip-Flop With Subnanosecond Data Backup Time for Fine-Grain Power Gating. - Kazemi, Mohammad; Ipek, Engin; Friedman, Eby G. (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Multistate Register Based on Resistive RAM. - Patel, Ravi; Kvatinsky, Shahar; Friedman, Eby G.; Kolodny, Avinoam (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits. - Savidis, Ioannis; Vaisband, Boris; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Architecting a MOS current mode logic (MCML) processor for fast, low noise and energy-efficient computing in the near-threshold regime. - Bai, Yuxin; Song, Yanwei; Bojnordi, Mahdi Nazm; Shapiro, Alexander E.; Ipek, Engin; Friedman, Eby G. (2015)

3-D floorplanning algorithm to minimize thermal interactions. - Vaisband, Boris; Friedman, Eby G. (2015)

Inductive coupling effects in large TSV arrays. - Xu, Kan; Friedman, Eby G. (2015)

Memristor-Based Multithreading. - Kvatinsky, Shahar; Nacson, Yuval H.; Etsion, Yoav; Friedman, Eby G.; Kolodny, Avinoam; Weiser, Uri C. (IEEE Comput. Archit. Lett., 2014)

2T-1R STT-MRAM memory cells for enhanced on/off current ratio. - Patel, Ravi; Ipek, Engin; Friedman, Eby G. (Microelectron. J., 2014)

Logic operations in memory using a memristive Akers array. - Levy, Yifat; Bruck, Jehoshua; Cassuto, Yuval; Friedman, Eby G.; Kolodny, Avinoam; Yaakobi, Eitan; Kvatinsky, Shahar (Microelectron. J., 2014)

MAGIC - Memristor-Aided Logic. - Kvatinsky, Shahar; Belousov, Dmitry; Liman, Slavik; Satat, Guy; Wald, Nimrod; Friedman, Eby G.; Kolodny, Avinoam; Weiser, Uri C. (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. - Kvatinsky, Shahar; Satat, Guy; Wald, Nimrod; Friedman, Eby G.; Kolodny, Avinoam; Weiser, Uri C. (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Digitally Controlled Pulse Width Modulator for On-Chip Power Management. - Vaisband, Inna; Azhar, Mahmood J.; Friedman, Eby G.; Köse, Selçuk (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Thermal conduction path analysis in 3-D ICs. - Vaisband, Boris; Savidis, Ioannis; Friedman, Eby G. (2014)

Computationally efficient clustering of power supplies in heterogeneous real time systems. - Vaisband, Inna; Friedman, Eby G. (2014)

Field driven STT-MRAM cell for reduced switching latency and energy. - Patel, Ravi; Ipek, Engin; Friedman, Eby G. (2014)

Sub-crosspoint RRAM decoding for improved area efficiency. - Patel, Ravi; Friedman, Eby G. (2014)

Dynamic power management with power network-on-chip. - Vaisband, Inna; Friedman, Eby G. (2014)

Power network-on-chip for scalable power delivery. - Vaisband, Inna; Friedman, Eby G. (2014)

Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks. - Abdelhadi, Ameer; Ginosar, Ran; Kolodny, Avinoam; Friedman, Eby G. (Integr., 2013)

Power Noise in TSV-Based 3-D Integrated Circuits. - Savidis, Ioannis; Köse, Selçuk; Friedman, Eby G. (IEEE J. Solid State Circuits, 2013)

Data bus swizzling in TSV-based three-dimensional integrated circuits. - Ge, Shen; Friedman, Eby G. (Microelectron. J., 2013)

TEAM: ThrEshold Adaptive Memristor Model. - Kvatinsky, Shahar; Friedman, Eby G.; Kolodny, Avinoam; Weiser, Uri C. (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Active Filter-Based Hybrid On-Chip DC-DC Converter for Point-of-Load Voltage Regulation. - Köse, Selçuk; Tam, Simon; Pinzon, Sally; McDermott, Bruce; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Power Network Optimization Based on Link Breaking Methodology. - Jakushokas, Renatas; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2013)

AC-DIMM: associative computing with STT-MRAM. - Guo, Qing; Guo, Xiaochen; Patel, Ravi; Ipek, Engin; Friedman, Eby G. (2013)

Digitally controlled wide range pulse width modulator for on-chip power supplies. - Köse, Selçuk; Vaisband, Inna; Friedman, Eby G. (2013)

Current profile of a microcontroller to determine electromagnetic emissions. - Köse, Selçuk; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (2013)

Distributed On-Chip Power Delivery. - Köse, Selçuk; Friedman, Eby G. (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Efficient algorithms for fast IR drop analysis exploiting locality. - Köse, Selçuk; Friedman, Eby G. (Integr., 2012)

Utilizing interdependent timing constraints to enhance robustness in synchronous circuits. - Salman, Emre; Friedman, Eby G. (Microelectron. J., 2012)

Multi-aggressor capacitive and inductive coupling noise modeling and mitigation. - Vishnyakov, Victoria; Friedman, Eby G.; Kolodny, Avinoam (Microelectron. J., 2012)

Distributed power delivery for energy efficient and low power systems. - Köse, Selçuk; Friedman, Eby G. (2012)

Link breaking methodology: mitigating noise within power networks. - Jakushokas, Renatas; Friedman, Eby G. (2012)

Energy metrics for power efficient crosslink and mesh topologies. - Vaisband, Inna; Friedman, Eby G.; Ginosar, Ran; Kolodny, Avinoam (2012)

An area efficient on-chip hybrid voltage regulator. - Köse, Selçuk; Friedman, Eby G.; Tarn, Simon; Pinzon, Sally; McDermott, Bruce (2012)

STT-MRAM memory cells with enhanced on/off ratio. - Patel, Ravi; Ipek, Engin; Friedman, Eby G. (2012)

Arithmetic encoding for memristive multi-bit storage. - Patel, Ravi; Friedman, Eby G. (2012)

Thermal analysis of oxide-confined VCSEL arrays. - Wang, Jinhui; Savidis, Ioannis; Friedman, Eby G. (Microelectron. J., 2011)

Effective Resistance of a Two Layer Mesh. - Köse, Selçuk; Friedman, Eby G. (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Multi-Layer Interdigitated Power Distribution Networks. - Jakushokas, Renatas; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits. - Rosenfeld, Jonathan; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Shielding Methodologies in the Presence of Power/Ground Noise. - Köse, Selçuk; Salman, Emre; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Linear and Switch-Mode Conversion in 3-D Circuits. - Rosenfeld, Jonathan; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Clock Distribution Networks in 3-D Integrated Systems. - Pavlidis, Vasilis F.; Savidis, Ioannis; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Fast algorithms for IR voltage drop analysis exploiting locality. - Köse, Selçuk; Friedman, Eby G. (2011)

Memristor-based IMPLY logic design procedure. - Kvatinsky, Shahar; Kolodny, Avinoam; Weiser, Uri C.; Friedman, Eby G. (2011)

Clock distribution models of 3-D integrated systems. - Savidis, Ioannis; Pavlidis, Vasilis F.; Friedman, Eby G. (2011)

Distributed power network co-design with on-chip power supplies and decoupling capacitors. - Köse, Selçuk; Friedman, Eby G. (2011)

Physical Analysis of NoC Topologies for 3-D Integrated Systems. - Pavlidis, Vasilis F.; Friedman, Eby G. (2011)

Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect. - Morgenshtein, Arkadiy; Friedman, Eby G.; Ginosar, Ran; Kolodny, Avinoam (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Resource Based Optimization for Simultaneous Shield and Repeater Insertion. - Jakushokas, Renatas; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]. - Morgenshtein, Arkadiy; Friedman, Eby G.; Ginosar, Ran; Kolodny, Avinoam (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Timing-driven variation-aware nonuniform clock mesh synthesis. - Abdelhadi, Ameer; Ginosar, Ran; Kolodny, Avinoam; Friedman, Eby G. (2010)

Line width optimization for interdigitated power/ground networks. - Jakushokas, Renatas; Friedman, Eby G. (2010)

On-chip point-of-load voltage regulator for distributed power supplies. - Köse, Selçuk; Friedman, Eby G. (2010)

Methodology to achieve higher tolerance to delay variations in synchronous circuits. - Salman, Emre; Friedman, Eby G. (2010)

Efficiency optimization of integrated DC-DC buck converters. - Sizikov, Gregory; Kolodny, Avinoam; Friedman, Eby G.; Zelikson, Michael (2010)

An intra-chip free-space optical interconnect. - Xue, Jing; Garg, Alok; Ciftcioglu, Berkehan; Hu, Jianyun; Wang, Shang; Savidis, Ioannis; Jain, Manish; Berman, Rebecca; Liu, Peng; Huang, Michael C.; Wu, Hui; Friedman, Eby G.; et al. (2010)

Globally integrated power and clock distribution network. - Jakushokas, Renatas; Friedman, Eby G. (2010)

Compact substrate models for efficient noise coupling and signal isolation analysis. - Jakushokas, Renatas; Salman, Emre; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L.; Recker, Cynthia L. (2010)

An area efficient fully monolithic hybrid voltage regulator. - Köse, Selçuk; Friedman, Eby G. (2010)

Methodology for multi-layer interdigitated power and ground network design. - Jakushokas, Renatas; Friedman, Eby G. (2010)

Fast algorithms for power grid analysis based on effective resistance. - Köse, Selçuk; Friedman, Eby G. (2010)

Simultaneous co-design of distributed on-chip power supplies and decoupling capacitors. - Köse, Selçuk; Friedman, Eby G. (2010)

Transient Response of a Distributed RLC Interconnect Based on Direct Pole Extraction. - Chen, Guoqing; Friedman, Eby G. (J. Circuits Syst. Comput., 2009)

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits. - Pavlidis, Vasilis F.; Friedman, Eby G. (Proc. IEEE, 2009)

Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance. - Salman, Emre; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Inductance Model of Interdigitated Power and Ground Distribution Networks. - Jakushokas, Renatas; Friedman, Eby G. (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology. - Rosenfeld, Jonathan; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits. - Salman, Emre; Jakushokas, Renatas; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling. - Salman, Emre; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Contact merging algorithm for efficient substrate noise analysis in large scale circuits. - Salman, Emre; Jakushokas, Renatas; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (2009)

Simultaneous shield and repeater insertion. - Jakushokas, Renatas; Friedman, Eby G. (2009)

Design challenges in high performance three-dimensional circuits. - Friedman, Eby G. (2009)

Power efficient tree-based crosslinks for skew reduction. - Vaisband, Inna; Ginosar, Ran; Kolodny, Avinoam; Friedman, Eby G. (2009)

Minimizing Noise Via Shield and Repeater Insertion. - Jakushokas, Renatas; Friedman, Eby G. (2009)

Shielding Methodologies in the Presence of Power/Ground Noise. - Köse, Selçuk; Salman, Emre; Friedman, Eby G. (2009)

On-chip DC-DC converters for three-dimensional ICs. - Rosenfeld, Jonathan; Friedman, Eby G. (2009)

Timing-driven via placement heuristics for three-dimensional ICs. - Pavlidis, Vasilis F.; Friedman, Eby G. (Integr., 2008)

Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis. - Chen, Guoqing; Friedman, Eby G. (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Effective Radii of On-Chip Decoupling Capacitors. - Popovich, Mikhail; Sotman, Michael; Kolodny, Avinoam; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2008)

On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits. - Popovich, Mikhail; Friedman, Eby G.; Sotman, Michael; Kolodny, Avinoam (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs. - Popovich, Mikhail; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Clock distribution networks for 3-D ictegrated Circuits. - Pavlidis, Vasilis F.; Savidis, Ioannis; Friedman, Eby G. (2008)

Input port reduction for efficient substrate extraction in large scale IC's. - Salman, Emre; Jakushokas, Renatas; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (2008)

Electrical modeling and characterization of 3-D vias. - Savidis, Ioannis; Friedman, Eby G. (2008)

Equivalent rise time for resonance in power/ground noise estimation. - Salman, Emre; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (2008)

Transient simulation of on-chip transmission lines via exact pole extraction. - Chen, Guoqing; Friedman, Eby G. (2008)

Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates. - Salman, Emre; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (2008)

Timing optimization in logic with interconnect. - Morgenshtein, Arkadiy; Friedman, Eby G.; Ginosar, Ran; Kolodny, Avinoam (2008)

Pseudo-random clocking to enhance signal integrity. - Köse, Selçuk; Salman, Emre; Ignjatovic, Zeljko; Friedman, Eby G. (2008)

Nanoscale on-chip decoupling capacitors. - Popovich, Mikhail; Friedman, Eby G. (2008)

A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators. - Lavzin, Alexander; Kozak, Mücahit; Friedman, Eby G. (2008)

Physical Design Issues in 3-D Integrated Technologies. - Pavlidis, Vasilis F.; Friedman, Eby G. (2008)

Predictions of CMOS compatible on-chip optical interconnect. - Chen, Guoqing; Chen, Hui; Haurylau, Mikhail; Nelson, Nicholas; Albonesi, David H.; Fauchet, Philippe M.; Friedman, Eby G. (Integr., 2007)

Wire shaping of RLC interconnects. - El-Moursy, Magdy A.; Friedman, Eby G. (Integr., 2007)

Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis. - Salman, Emre; Dasdan, Ali; Taraporevala, Feroze; Küçükçakar, Kayhan; Friedman, Eby G. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Design Methodology for Global Resonant H-Tree Clock Distribution Networks. - Rosenfeld, Jonathan; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2007)

3-D Topologies for Networks-on-Chip. - Pavlidis, Vasilis F.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs. - Popovich, Mikhail; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (2007)

Quasi-Resonant Interconnects: A Low Power Design Methodology. - Rosenfeld, Jonathan; Friedman, Eby G. (2007)

Substrate Noise Reduction Based On Noise Aware Cell Design. - Salman, Emre; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (2007)

On-chip optical interconnect for reduced delay uncertainty. - Chen, Guoqing; Chen, Hui; Haurylau, Mikhail; Nelson, Nicholas; Albonesi, David H.; Fauchet, Philippe M.; Friedman, Eby G. (2007)

Sizing CMOS inverters with Miller Effect and Threshold voltage Variations. - Andreev, Boris D.; Titlebaum, Edward L.; Friedman, Eby G. (J. Circuits Syst. Comput., 2006)

On-chip test circuit for measuring substrate and line-to-line coupling noise. - Xu, Weize; Friedman, Eby G. (IEEE J. Solid State Circuits, 2006)

Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. - Chen, Guoqing; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Decoupling capacitors for multi-voltage power distribution systems. - Popovich, Mikhail; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Crosstalk modeling for coupled RLC interconnects with application to shield insertion. - Zhang, Junmou; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Maximum effective distance of on-chip decoupling capacitors in power distribution grids. - Popovich, Mikhail; Friedman, Eby G.; Sotman, Michael; Kolodny, Avinoam; Secareanu, Radu M. (2006)

Sensitivity evaluation of global resonant H-tree clock distribution networks. - Rosenfeld, Jonathan; Friedman, Eby G. (2006)

Effective capacitance of RLC loads for estimating short-circuit power. - Chen, Guoqing; Friedman, Eby G. (2006)

Optimum wire tapering for minimum power dissipation in RLC interconnects. - El-Moursy, Magdy A.; Friedman, Eby G. (2006)

Via placement for minimum interconnect delay in three-dimensional (3D) circuits. - Pavlidis, Vasilis F.; Friedman, Eby G. (2006)

Design methodology for global resonant H-tree clock distribution networks. - Rosenfeld, Jonathan; Friedman, Eby G. (2006)

On-die decoupling capacitance: frequency domain analysis of activity radius. - Sotman, Michael; Kolodny, Avinoam; Popovich, Mikhail; Friedman, Eby G. (2006)

Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times. - Salman, Emre; Friedman, Eby G.; Dasdan, Ali; Taraporevala, Feroze; Küçükçakar, Kayhan (2006)

3-D Topologies for Networks-on-Chip. - Pavlidis, Vasilis F.; Friedman, Eby G. (2006)

Substrate and Ground Noise Interactions in Mixed-Signal Circuits. - Salman, Emre; Friedman, Eby G.; Secareanu, Radu M. (2006)

Monolithic voltage conversion in low-voltage CMOS technologies. - Kursun, Volkan; De, Vivek; Friedman, Eby G.; Narendra, Siva G. (Microelectron. J., 2005)

An RLC interconnect model based on fourier analysis. - Chen, Guoqing; Friedman, Eby G. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Shielding effect of on-chip interconnect inductance. - El-Moursy, Magdy A.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Exponentially tapered H-tree clock distribution networks. - El-Moursy, Magdy A.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2005)

On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. - Popovich, Mikhail; Friedman, Eby G.; Sotman, Michael; Kolodny, Avinoam (2005)

Interconnect delay minimization through interlayer via placement in 3-D ICs. - Pavlidis, Vasilis F.; Friedman, Eby G. (2005)

Cascode buffer for monolithic voltage conversion operating at high input supply voltages. - Kursun, Volkan; Schrom, Gerhard; De, Vivek; Friedman, Eby G.; Narendra, Siva G. (2005)

Low power repeaters driving RLC interconnects with delay and bandwidth constraints. - Chen, Guoqing; Friedman, Eby G. (2005)

Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment. - Secareanu, Radu M.; Banerjee, Suman K.; Hartin, Olin L.; Fernandez, Virgilio; Friedman, Eby G. (2005)

Noise coupling in multi-voltage power distribution systems with decoupling capacitors. - Popovich, Mikhail; Friedman, Eby G. (2005)

Electrical and optical on-chip interconnects in scaled microprocessors. - Chen, Guoqing; Chen, Hui; Haurylau, Mikhail; Nelson, Nicholas; Fauchet, Philippe M.; Friedman, Eby G.; Albonesi, David H. (2005)

A Fourier series-based RLC interconnect model for periodic signals. - Chen, Guoqing; Friedman, Eby G. (2005)

Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems. - Popovich, Mikhail; Friedman, Eby G. (2005)

Predictions of CMOS compatible on-chip optical interconnect. - Chen, Guoqing; Chen, Hui; Haurylau, Mikhail; Nelson, Nicholas; Fauchet, Philippe M.; Friedman, Eby G.; Albonesi, David H. (2005)

On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits. - Popovich, Mikhail; Friedman, Eby G.; Secareanu, Radu M.; Hartin, Olin L. (2005)

Optimum wire sizing of RLC interconnect with repeaters . - El-Moursy, Magdy A.; Friedman, Eby G. (Integr., 2004)

Low-voltage-swing monolithic dc-dc conversion. - Kursun, Volkan; Narendra, Siva G.; De, Vivek K.; Friedman, Eby G. (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

Substrate coupling in digital circuits in mixed-signal smart-power systems. - Secareanu, Radu M.; Warner, Scott; Seabridge, Scott; Burke, Cathie; Becerra, Juan; Watrobski, Thomas E.; Morton, Christopher; Staub, William; Tellier, Thomas; Kourtev, Ivan S.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Scaling trends of on-chip power distribution noise. - Mezhiba, Andrey V.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Sleep switch dual threshold Voltage domino logic with reduced standby leakage current. - Kursun, Volkan; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Impedance characteristics of power distribution grids in nanoscale integrated circuits. - Mezhiba, Andrey V.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Power characteristics of inductive interconnect. - El-Moursy, Magdy A.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Complex +/-1 Multiplier Based on Signed-Binary Transformations. - Andreev, Boris D.; Titlebaum, Edward L.; Friedman, Eby G. (J. VLSI Signal Process., 2004)

A bulk-driven CMOS OTA with 68 dB DC gain. - Rosenfeld, Jonathan; Kozak, Mücahit; Friedman, Eby G. (2004)

A 250 MHz delta-sigma modulator for low cost ultrasound/sonar beamforming applications. - Shem-Tov, Boaz; Kozak, Mücahit; Friedman, Eby G. (2004)

Impedance characteristics of decoupling capacitors in multi-power distribution systems. - Popovich, Mikhail; Friedman, Eby G. (2004)

Challenges in ultra deep submicrometer high performance VLSI circuits. - Friedman, Eby G. (2004)

Buffer sizing for delay uncertainty induced by process variations. - Velenis, Dimitrios; Sundaresha, Ramyashree; Friedman, Eby G. (2004)

A high-speed CMOS op-amp design technique using negative Miller capacitance. - Shem-Tov, Boaz; Kozak, Mücahit; Friedman, Eby G. (2004)

Low power flexible Rake receivers for WCDMA. - Andreev, Boris D.; Titlebaum, Edward L.; Friedman, Eby G. (2004)

Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage. - Kursun, Volkan; Friedman, Eby G. (2004)

Decoupling technique and crosstalk analysis for coupled RLC interconnects. - Zhang, Junmou; Friedman, Eby G. (2004)

Effect of shield insertion on reducing crosstalk noise between coupled interconnects. - Zhang, Junmou; Friedman, Eby G. (2004)

Exponentially tapered H-tree clock distribution networks. - El-Moursy, Magdy A.; Friedman, Eby G. (2004)

A low power thyristor-based CMOS programmable delay element. - Zhang, Junmou; Cooper, Simon R.; LaPietra, Andrew R.; Mattern, Michael W.; Guidash, Robert M.; Friedman, Eby G. (2004)

Design and simulation of Fractional-N PLL frequency synthesizers. - Kozak, Mücahit; Friedman, Eby G. (2004)

Forward body biased keeper for enhanced noise immunity in domino logic circuits. - Kursun, Volkan; Friedman, Eby G. (2004)

Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. - Kursun, Volkan; Friedman, Eby G. (2004)

High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. - Kursun, Volkan; Narendra, Siva G.; De, Vivek; Friedman, Eby G. (2004)

Buffer Sizing for Crosstalk Induced Delay Uncertainty. - Velenis, Dimitrios; Friedman, Eby G. (2004)

Clock tree layout design for reduced delay uncertainty. - Velenis, Dimitrios; Papaefthymiou, Marios C.; Friedman, Eby G. (2004)

Decoupling capacitors for power distribution systems with multiple power supply voltages. - Popovich, Mikhail; Friedman, Eby G. (2004)

Low power repeaters driving RC interconnects with delay and bandwidth constraints. - Chen, Guoqing; Friedman, Eby G. (2004)

Mutual inductance modeling for multiple RLC interconnects with application to shield insertion. - Zhang, Junmou; Friedman, Eby G. (2004)

Dynamically Tuning Processor Resources with Adaptive Processing. - Albonesi, David H.; Balasubramonian, Rajeev; Dropsho, Steve; Dwarkadas, Sandhya; Friedman, Eby G.; Huang, Michael C.; Kursun, Volkan; Magklis, Grigorios; Scott, Michael L.; Semeraro, Greg; Bose, Pradip; Buyuktosunoglu, Alper; et al. (Computer, 2003)

On the Extraction of On-Chip Inductance. - Ismail, Yehea I.; Friedman, Eby G. (J. Circuits Syst. Comput., 2003)

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. - Kursun, Volkan; Narendra, Siva G.; De, Vivek; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Domino logic with variable threshold voltage keeper. - Kursun, Volkan; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Reduced Delay Uncertainty in High Performance Clock Distribution Networks. - Velenis, Dimitrios; Papaefthymiou, Marios C.; Friedman, Eby G. (2003)

Optimum wire sizing of RLC interconnect with repeaters. - El-Moursy, Magdy A.; Friedman, Eby G. (2003)

Shielding effect of on-chip interconnect inductance. - El-Moursy, Magdy A.; Friedman, Eby G. (2003)

Orthogonal code generator for 3G wireless transceivers. - Andreev, Boris D.; Titlebaum, Edward L.; Friedman, Eby G. (2003)

Power characteristics of inductive interconnect. - El-Moursy, Magdy A.; Friedman, Eby G. (2003)

Inductive interconnect width optimization for low power. - El-Moursy, Magdy A.; Friedman, Eby G. (2003)

Electrical characteristics of multi-layer power distribution grids. - Mezhiba, Andrey V.; Friedman, Eby G. (2003)

Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. - Kursun, Volkan; Narendra, Siva G.; De, Vivek; Friedman, Eby G. (2003)

Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic. - Andreev, Boris D.; Titlebaum, Edward L.; Friedman, Eby G. (2003)

Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. - Velenis, Dimitrios; Tang, Kevin T.; Kourtev, Ivan S.; Adler, Victor; Baez, Franklin; Friedman, Eby G. (J. Circuits Syst. Comput., 2002)

Inductance Effects in RLC Trees. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (J. Circuits Syst. Comput., 2002)

DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect. - Ismail, Yehea I.; Friedman, Eby G. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Retiming and clock scheduling for digital circuit optimization. - Liu, Xun; Papaefthymiou, Marios C.; Friedman, Eby G. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Simultaneous switching noise in on-chip CMOS power distribution networks. - Tang, Kevin T.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Inductive properties of high-performance power distribution grids. - Mezhiba, Andrey V.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Properties of on-chip inductive current loops. - Mezhiba, Andrey V.; Friedman, Eby G. (2002)

Low swing dual threshold voltage domino logic. - Kursun, Volkan; Friedman, Eby G. (2002)

Efficient implementation of a complex ±1 multiplier. - Andreev, Boris D.; Friedman, Eby G.; Titlebaum, Edward L. (2002)

Inductance/area/resistance tradeoffs in high performance power distribution grids. - Mezhiba, Andrey V.; Friedman, Eby G. (2002)

A substrate noise circuit for accurately testing mixed-signal ICs. - Xu, Weize; Friedman, Eby G. (2002)

Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits. - Mader, Roy; Friedman, Eby G.; Litman, Ami; Kourtev, Ivan S. (2002)

Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits. - Mezhiba, Andrey V.; Friedman, Eby G. (2002)

Managing static leakage energy in microprocessor functional units. - Dropsho, Steve; Kursun, Volkan; Albonesi, David H.; Dwarkadas, Sandhya; Friedman, Eby G. (2002)

Scaling trends of on-chip Power distribution noise. - Mezhiba, Andrey V.; Friedman, Eby G. (2002)

Clock distribution networks in synchronous digital integrated circuits. - Friedman, Eby G. (Proc. IEEE, 2001)

Exploiting the on-chip inductance in high-speed clock distribution networks. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (IEEE Trans. Very Large Scale Integr. Syst., 2001)

A comparative study of the behavior of NMOS and CMOS digital circuits under substrate noise. - Secareanu, Radu M.; Warner, Scott; Seabridge, Scott; Burke, Cathie; Watrobski, Thomas E.; Morton, Christopher; Staub, William; Tellier, Thomas; Friedman, Eby G. (2001)

Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling. - Velenis, Dimitrios; Tang, Kevin T.; Kourtev, Ivan S.; Adler, Victor; Baez, Franklin; Friedman, Eby G. (2001)

A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. - Velenis, Dimitrios; Friedman, Eby G.; Papaefthymiou, Marios C. (2001)

Estimation of transient voltage fluctuations in the CMOS-based power distribution networks. - Tang, Kevin T.; Friedman, Eby G. (2001)

Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections. - Tang, Kevin T.; Friedman, Eby G. (Integr., 2000)

Equivalent Elmore delay for RLC trees. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. - Ismail, Yehea I.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Transparent repeaters. - Secareanu, Radu M.; Friedman, Eby G. (2000)

Noise estimation due to signal activity for capacitively coupled CMOS logic gates. - Tang, Kevin T.; Friedman, Eby G. (2000)

Transient analysis of a CMOS inverter driving resistive interconnect. - Tang, Kevin T.; Friedman, Eby G. (2000)

Physical design to improve the noise immunity of digital circuits in a mixed-signal smart-power system. - Secareanu, Radu M.; Warner, Scott; Seabridge, Scott; Burke, Cathie; Watrobski, Thomas E.; Morton, Christopher; Staub, William; Tellier, Thomas; Friedman, Eby G. (2000)

Delay and power expressions characterizing a CMOS inverter driving an RLC load. - Tang, Kevin T.; Friedman, Eby G. (2000)

Sensitivity of interconnect delay to on-chip inductance. - Ismail, Yehea I.; Friedman, Eby G. (2000)

Figures of merit to characterize the importance of on-chip inductance. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Maximizing Performance by Retiming and Clock Skew Scheduling. - Liu, Xun; Papaefthymiou, Marios C.; Friedman, Eby G. (1999)

Equivalent Elmore Delay for RLC Trees. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (1999)

Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. - Ismail, Yehea I.; Friedman, Eby G. (1999)

Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. - Liu, Xun; Papaefthymiou, Marios C.; Friedman, Eby G. (1999)

Inductance Effects in RLC Trees. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (1999)

Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. - Secareanu, Radu M.; Kourtev, Ivan S.; Becerra, Juan; Watrobski, Thomas E.; Morton, Christopher; Staub, William; Tellier, Thomas; Friedman, Eby G. (1999)

Clock skew scheduling for improved reliability via quadratic programming. - Kourtev, Ivan S.; Friedman, Eby G. (1999)

Repeater insertion in tree structured inductive interconnect. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (1999)

Exploiting hysteresis in a CMOS buffer. - Secareanu, Radu M.; Adler, Victor; Friedman, Eby G. (1999)

Peak crosstalk noise estimation in CMOS VLSI circuits. - Tang, Kevin T.; Friedman, Eby G. (1999)

Signal waveform characterization in RLC trees. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (1999)

A universal CMOS voltage interface circuit. - Secareanu, Radu M.; Friedman, Eby G.; Becerra, Juan; Warner, Scott (1999)

A high precision CMOS current mirror/divider. - Secareanu, Radu M.; Friedman, Eby G. (1999)

Repeater insertion in RLC lines for minimum propagation delay. - Ismail, Yehea I.; Friedman, Eby G. (1999)

Peak noise prediction in loosely coupled interconnect [VLSI circuits]. - Tang, Kevin T.; Friedman, Eby G. (1999)

Interconnect coupling noise in CMOS VLSI circuits. - Tang, Kevin T.; Friedman, Eby G. (1999)

System Timing. - Kourtev, Ivan S.; Friedman, Eby G. (1999)

Automated Synthesis of Skew-Based Clock Distribution Networks. - Neves, José Luis; Friedman, Eby G. (VLSI Design, 1998)

Figures of Merit to Characterize the Importance of On-Chip Inductance. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (1998)

Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (1998)

A repeater timing model and insertion algorithm to reduce delay in RC tree structures. - Adler, Victor; Friedman, Eby G. (1998)

Transient power in CMOS gates driving LC transmission lines. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (1998)

Power dissipated by CMOS gates driving lossless transmission lines. - Ismail, Yehea I.; Friedman, Eby G.; Neves, José Luis (1998)

Incorporating interconnect, register, and clock distribution delays into the retiming process. - Soyata, Tolga; Friedman, Eby G.; Mulligan, James H., Jr. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

High Performance Clock Distribution Networks. - Friedman, Eby G. (J. VLSI Signal Process., 1997)

Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations. - Neves, José Luis; Friedman, Eby G. (J. VLSI Signal Process., 1997)

Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits. - Gaj, Kris; Friedman, Eby G.; Feldman, Marc J. (J. VLSI Signal Process., 1997)

Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew. - Neves, José Luis; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Optimal Clock Skew Scheduling Tolerant to Process Variations. - Neves, José Luis; Friedman, Eby G. (1996)

Design of tapered buffers with local interconnect capacitance. - Cherkauer, Brian S.; Friedman, Eby G. (IEEE J. Solid State Circuits, 1995)

A unified design methodology for CMOS tapered buffers. - Cherkauer, Brian S.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 1995)

Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks. - Neves, José Luis; Friedman, Eby G. (1995)

Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. - Soyata, Tolga; Friedman, Eby G.; Mulligan, James H., Jr. (1995)

Channel width tapering of serially connected MOSFET's with emphasis on power dissipation. - Cherkauer, Brian S.; Friedman, Eby G. (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Retiming with non-zero clock skew, variable register, and interconnect delay. - Soyata, Tolga; Friedman, Eby G. (1994)

Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS. - Friedman, Eby G.; Kang, Sung-Mo; Vittoz, Eric A.; Allstot, David J.; Harris, Erik P.; Yan, Ran-Hong (1994)

Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design. - Cherkauer, Brian S.; Friedman, Eby G. (1994)

Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew. - Neves, José Luis; Friedman, Eby G. (1994)

Clock Distribution Design in VLSI Circuits. An Overview. - Friedman, Eby G. (1993)

Integration of Clock Skew and Register Delays into a Retiming Algorithm. - Soyata, Tolga; Friedman, Eby G.; Mulligan, James H., Jr. (1993)

The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs. - Cherkauer, Brian S.; Friedman, Eby G. (1993)

Clock frequency and latency in synchronous digital systems. - Friedman, Eby G.; Mulligan, James H., Jr. (IEEE Trans. Signal Process., 1991)