4.6 A 0.8V, 31ppm/°C, -40dB DC-to-GHz Power-Supply-Rejection Standard-Vth Core-MOS-Only Voltage Reference with a 294\(μ\)m\(^2\)Area - Bei-Shing Lien; Szu-Lin Liu; Wei-Lin Lai; Yi-Chen Lu; Yung-Chow Peng; Kenny Cheng-Hsiang Hsieh (IEEE International Solid-State Circuits Conference, ISSCC 2025, San Francisco, CA, USA, February 16-20, 2025, 2025)

3.8 A 0.65V 900\(μ\)m\(^2\) BEoL RC-Based Temperature Sensor with \(±\)1°C Inaccuracy from -25°C to 125°C - Bei-Shing Lien; Szu-Lin Liu; Wei-Lin Lai; Yi-Chen Lu; Yung-Chow Peng; Kenny Cheng-Hsiang Hsieh (IEEE International Solid-State Circuits Conference, ISSCC 2024, San Francisco, CA, USA, February 18-22, 2024, 2024)

Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process - Chu-En Hsia; Chin-Ho Chang; Yung-Shun Chen; Po-Yu Lai; Ching Lin Jen; Yung-Chow Peng; Shenggao Li (IEEE Symposium on VLSI Technology and Circuits 2024, Honolulu, HI, USA, June 16-20, 2024, 2024)

A 0.7V, 2.35% 3\(σ\)-Accuracy Bandgap Reference in 12nm CMOS - Yi-Wen Chen; Jaw-Juinn Horng; Chin-Ho Chang; Amit Kundu; Yung-Chow Peng; Mark Chen (IEEE International Solid- State Circuits Conference, ISSCC 2019, San Francisco, CA, USA, February 17-21, 2019, 2019)

An ultra-compact, untrimmed CMOS bandgap reference with 3\(σ\) inaccuracy of +0.64% in 16nm FinFET - Chin-Ho Chang; Jaw-Juinn Horng; Amit Kundu; Chih-Chiang Chang; Yung-Chow Peng (IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014, 2014)

A 0.7V resistive sensor with temperature/voltage detection function in 16nm FinFET technologies - Jaw-Juinn Horng; Szu-Lin Liu; Amit Kundu; Chin-Ho Chang; Chung-Hui Chen; Herman Chiang; Yung-Chow Peng (Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014, 2014)

An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter - Wen-Shen Chou; Tzu-Chi Huang; Yu-Huei Lee; Yao-Yi Yang; Yi-Ping Su; Ke-Horng Chen; Chen-Chih Huang; Ying-Hsi Lin; Chao-Cheng Lee; Kuei-Ann Wen; Ying-Chih Hsu; Yung-Chow Peng; et al. (IEEE J. Solid State Circuits, 2012)

55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter - Tzu-Chi Huang; Wen-Shen Chou; Yu-Huei Lee; Yao-Yi Yang; Ke-Horng Chen; Yung-Chow Peng; Fu-Lung Hsueh (Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011, 2011)

A 2.5-8Gb/s transceiver with 5-tap DFE and Second order CDR against 28-inch channel and 5000ppm SSC in 40nm CMOS technology - Wei-Chih Chen; Chien-Chun Tsai; Chih-Hsien Chang; Yung-Chow Peng; Fu-Lung Hsueh; Tsung-Hsin Yu; Jinn-Yeh Chien; Wen-Hung Huang; Chi-Chang Lu; Mu-Shan Lin; Chin-Ming Fu; Shu-Chun Yang; et al. (IEEE Custom Integrated Circuits Conference, CICC 2010, San Jose, California, USA, 19-22 September, 2010, Proceedings, 2010)

A BICMOS Limiting Amplifier for SONET OC-3 - Chen-Yi Huang; Yung-Chow Peng; Chrong-Kuang Wang (1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994, 1994)