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2000 – 2009
- 2009
[j4]Jason Cong, Karthik Gururaj, Guoling Han, Wei Jiang:
Synthesis Algorithm for Application-Specific Homogeneous Processor Networks. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1318-1329 (2009)- [c13]Jason Cong, Karthik Gururaj, Guoling Han:
Synthesis of reconfigurable high-performance multicore systems. FPGA 2009: 201-208 - 2008
- [c12]Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann
, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer:
Exploring power management in multi-core systems. ASP-DAC 2008: 708-713 - [c11]Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman:
MC-Sim: an efficient simulation tool for MPSoC designs. ICCAD 2008: 364-371 - 2007
- [j3]Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski:
Accelerating Sequential Applications on CMPs Using Core Spilling. IEEE Trans. Parallel Distributed Syst. 18(8): 1094-1107 (2007) - [c10]Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han:
Performance modeling for early analysis of multi-core systems. CODES+ISSS 2007: 209-214 - [c9]Jason Cong, Guoling Han, Wei Jiang:
Synthesis of an application-specific soft multiprocessor system. FPGA 2007: 99-107 - 2006
- [j2]Jason Cong, Guoling Han, Zhiru Zhang:
Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(9): 986-997 (2006) - [c8]Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang:
Behavior and communication co-optimization for systems with sequential communication media. DAC 2006: 675-678 - [c7]Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang:
Platform-Based Behavior-Level and System-Level Synthesis. SoCC 2006: 199-202 - 2005
- [c6]Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng:
Bitwidth-aware scheduling and binding in high-level synthesis. ASP-DAC 2005: 856-861 - [c5]Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang:
Instruction set extension with shadow registers for configurable processors. FPGA 2005: 99-106 - [c4]Jason Cong, Guoling Han, Zhiru Zhang:
Architecture and compilation for data bandwidth improvement in configurable embedded processors. ICCAD 2005: 263-270 - 2004
- [j1]Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architecture and synthesis for on-chip multicycle communication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 550-564 (2004) - [c3]Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang:
Application-specific instruction generation for configurable processor architectures. FPGA 2004: 183-189 - 2003
- [c2]Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architecture and synthesis for multi-cycle on-chip communication. CODES+ISSS 2003: 77-78 - [c1]Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. ICCAD 2003: 536-543
Coauthor Index
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