HiPerNoC: A High-Performance Network-an-Chip for Flexible and Scalable FPGA-Based SmartNICs. - Zyla, Klajd; Liess, Marco; Wild, Thomas; Herkersdorf, Andreas (2025)

HW-FUTEX: Hardware-Assisted Futex Syscall. - Nolte, Lars; Twardzik, Tim; Jalier, Camille; Huang, Zhigang; Shi, Jiyuan; Wild, Thomas; Herkersdorf, Andreas (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Hardware Assist for Linux IPC on an FPGA Platform. - Nolte, Lars; Twardzik, Tim; Jalier, Camille; Shi, Jiyuan; Wild, Thomas; Herkersdorf, Andreas (2024)

HASIIL: Hardware-Assisted Scheduling to Improve IPC Latency in Linux. - Twardzik, Tim; Nolte, Lars; Jalier, Camille; Shi, Jiyuan; Wild, Thomas; Herkersdorf, Andreas (2024)

EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. - Schmidt, Patrick; Topko, Iuliia; Stammler, Matthias; Harbaum, Tanja; Becker, Jürgen; Berner, Rico; Ahmed, Omar; Jagielski, Jakub; Seidler, Thomas; Abel, Markus; Kreutzer, Marius; Kirschner, Maximilian; et al. (2024)

FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar. - Zyla, Klajd; Liess, Marco; Wild, Thomas; Herkersdorf, Andreas (2024)

ecoNIC: Saving Energy Through SmartNIC-Based Load Balancing of Mixed-Critical Ethernet Traffic. - Biersack, Franz; Liess, Marco; Absmann, Markus; Lotter, Fabiana; Wild, Thomas; Herkersdorf, Andreas (2024)

XCS with dynamic sized experience replay for memory constrained applications. - Surhonne, Anmol; Wensauer, Manuel; Maurer, Florian; Wild, Thomas; Herkersdorf, Andreas (2024)

QoS-Aware Dynamic Frequency Scaling for Mixed-Critical Systems based on Shielded Reinforcement Learning. - Maurer, Florian; Meidinger, Michael; Lu, Yiming; Hallermeier, Thomas; Surhonne, Anmol; Wild, Thomas; Herkersdorf, Andreas (2024)

FlexRoute: A Fast, Flexible and Priority-Aware Packet-Processing Design. - Zyla, Klajd; Liess, Marco; Wild, Thomas; Herkersdorf, Andreas (2024)

EPIC-Q: Equivalent-Policy Invariant Comparison Enhanced Transfer Q-learning for Run-Time SoC Performance-Power Optimization. - Surhonne, Anmol; Fawzi, Haitham S.; Maurer, Florian; Lenke, Oliver; Meidinger, Michael; Wild, Thomas; Herkersdorf, Andreas (2024)

HW-EPOLL: Hardware-Assisted User Space Event Notification for Epoll Syscall. - Nolte, Lars; Twardzik, Tim; Jalier, Camille; Shi, Jiyuan; Wild, Thomas; Herkersdorf, Andreas (2024)

FlexCross: High-Speed and Flexible Packet Processing via a Crosspoint-Queued Crossbar. - Zyla, Klajd; Liess, Marco; Wild, Thomas; Herkersdorf, Andreas (CoRR, 2024)

Machine learning in run-time control of multicore processor systems. - Maurer, Florian; Thoma, Moritz; Surhonne, Anmol Prakash; Donyanavard, Bryan; Herkersdorf, Andreas (it Inf. Technol., 2023)

CoLeCTs: Cooperative Learning Classifier Tables for Resource Management in MPSoCs. - Zyla, Klajd; Maurer, Florian; Wild, Thomas; Herkersdorf, Andreas (2023)

HAWEN: Hardware Accelerator for Thread Wake-Ups in Linux Event Notification. - Nolte, Lars; Twardzik, Tim; Jalier, Camille; Huang, Zhigang; Shi, Jiyuan; Kowalsky, Clara; Wild, Thomas; Herkersdorf, Andreas (2023)

Information Processing Factory 2.0 - Self-awareness for Autonomous Collaborative Systems. - Sperling, Nora; Bendrick, Alex; Stöhrmann, Dominik; Ernst, Rolf; Donyanavard, Bryan; Maurer, Florian; Lenke, Oliver; Surhonne, Anmol; Herkersdorf, Andreas; Amer, Walaa; Melo, Caio Batista de; Chen, Ping-Xiang; et al. (2023)

LCT-DER: Learning Classifier Table with Dynamic-Sized Experience Replay for Run-time SoC Performance-Power Optimization. - Surhonne, Anmol; Maurer, Florian; Wild, Thomas; Herkersdorf, Andreas (2023)

LCT-TL : Learning Classifier Table (LCT) with Transfer Learning for runtime SoC performance-power optimization. - Surhonne, Anmol; Maurer, Florian; Wild, Thomas; Herkersdorf, Andreas (2023)

X-MAPE: Extending 6G-Connected Self-Adaptive Systems with Reflexive Actions. - Liess, Marco; Demicoli, Julian; Tiedje, Tobias; Lohrmann, Matthias; Nickel, Matthias; Luniak, M.; Prousalis, Dimitrios A.; Wild, Thomas; Tetzlaff, Ronald; Göhringer, Diana; Mayr, Christian; Bock, Karlheinz; et al. (2023)

Priority-aware Inter-Server Receive Side Scaling. - Biersack, Franz; Holzinger, Kilian; Stubbe, Henning; Wild, Thomas; Carle, Georg; Herkersdorf, Andreas (2023)

FlexPipe: Fast, Flexible and Scalable Packet Processing for High-Performance SmartNICs. - Zyla, Klajd; Liess, Marco; Wild, Thomas; Herkersdorf, Andreas (2023)

Autonomous Systems, Trust, and Guarantees. - Taherinejad, Nima; Herkersdorf, Andreas; Jantsch, Axel (IEEE Des. Test, 2022)

Fine-Grained Power Modeling of Multicore Processors Using FFNNs. - Sagi, Mark; Doan, Nguyen Anh Vu; Fasfous, Nael; Wild, Thomas; Herkersdorf, Andreas (Int. J. Parallel Program., 2022)

The Self-Aware Information Processing Factory Paradigm for Mixed-Critical Multiprocessing. - Rambo, Eberle A.; Donyanavard, Bryan; Seo, Minjun; Maurer, Florian; Kadeed, Thawra; Melo, Caio Batista de; Maity, Biswadip; Surhonne, Anmol; Herkersdorf, Andreas; Kurdahi, Fadi J.; Dutt, Nikil D.; Ernst, Rolf (IEEE Trans. Emerg. Top. Comput., 2022)

GAE-LCT: A Run-Time GA-Based Classifier Evolution Method for Hardware LCT Controlled SoC Performance-Power Optimization. - Surhonne, Anmol; Doan, Nguyen Anh Vu; Maurer, Florian; Wild, Thomas; Herkersdorf, Andreas (2022)

SmartNIC-based Load Management and Network Health Monitoring for Time Sensitive Applications. - Holzinger, Kilian; Biersack, Franz; Stubbe, Henning; Mariño, Angela Gonzalez; Kane, Abdoul; Fons, Francesc; Zhang, Haigang; Wild, Thomas; Herkersdorf, Andreas; Carle, Georg (2022)

GLS Tracing: Gem5-based Low-intrusive Software Tracing. - Nolte, Lars; Twardzik, Tim; Jalier, Camille; Huang, Zhigang; Shi, Jiyuan; Wild, Thomas; Herkersdorf, Andreas (2022)

DySHARQ: Dynamic Software-Defined Hardware-Managed Queues for Tile-Based Architectures. - Rheindt, Sven; Maier, Sebastian; Pohle, Nora; Nolte, Lars; Lenke, Oliver; Schmaus, Florian; Wild, Thomas; Schröder-Preikschat, Wolfgang; Herkersdorf, Andreas (Int. J. Parallel Program., 2021)

DynaCo: Dynamic Coherence Management for Tiled Manycore Architectures. - Srivatsa, Akshay; Mansour, Mostafa; Rheindt, Sven; Gabriel, Dirk; Wild, Thomas; Herkersdorf, Andreas (Int. J. Parallel Program., 2021)

Exploring a Hybrid Voting-based Eviction Policy for Caches and Sparse Directories on Manycore Architectures. - Srivatsa, Akshay; Fasfous, Nael; Doan, Nguyen Anh Vu; Nagel, Sebastian; Wild, Thomas; Herkersdorf, Andreas (Microprocess. Microsystems, 2021)

Protection switching schemes and mapping strategies for fail-operational hard real-time NoCs. - Koenen, Max; Doan, Nguyen Anh Vu; Wild, Thomas; Herkersdorf, Andreas (Microprocess. Microsystems, 2021)

SEAMS: Self-Optimizing Runtime Manager for Approximate Memory Hierarchies. - Maity, Biswadip; Donyanavard, Bryan; Surhonne, Anmol; Rahmani, Amir M.; Herkersdorf, Andreas; Dutt, Nikil D. (ACM Trans. Embed. Comput. Syst., 2021)

Precise real-time monitoring of time-critical flows. - Holzinger, Kilian; Stubbe, Henning; Biersack, Franz; Mariño, Angela Gonzalez; Kane, Abdoul; Lluis, Francisco Fons; Zhang, Haigang; Wild, Thomas; Herkersdorf, Andreas; Carle, Georg (2021)

Long Short-Term Memory Neural Network-based Power Forecasting of Multi-Core Processors. - Sagi, Mark; Rapp, Martin; Khdr, Heba; Zhang, Yizhe; Fasfous, Nael; Doan, Nguyen Anh Vu; Wild, Thomas; Henkel, Jörg; Herkersdorf, Andreas (2021)

PEPERONI: Pre-Estimating the Performance of Near-Memory Integration. - Lenke, Oliver; Petri, Richard; Wild, Thomas; Herkersdorf, Andreas (2021)

Power- and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-Cores. - Rapp, Martin; Sagi, Mark; Pathania, Anuj; Herkersdorf, Andreas; Henkel, Jörg (IEEE Trans. Computers, 2020)

A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power. - Sagi, Mark; Doan, Nguyen Anh Vu; Rapp, Martin; Wild, Thomas; Henkel, Jörg; Herkersdorf, Andreas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Self-aware Cyber-Physical Systems. - Bellman, Kirstie L.; Landauer, Christopher; Dutt, Nikil D.; Esterle, Lukas; Herkersdorf, Andreas; Jantsch, Axel; Taherinejad, Nima; Lewis, Peter R.; Platzner, Marco; Tammemäe, Kalle (ACM Trans. Cyber Phys. Syst., 2020)

Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs. - Hu, Yong; Mettler, Marcel; Mueller-Gritschneder, Daniel; Wild, Thomas; Herkersdorf, Andreas; Schlichtmann, Ulf (ACM Trans. Design Autom. Electr. Syst., 2020)

Combinatorial Auctions for Temperature-Constrained Resource Management in Manycores. - Khdr, Heba; Shafique, Muhammad; Pagani, Santiago; Herkersdorf, Andreas; Henkel, Jörg (IEEE Trans. Parallel Distributed Syst., 2020)

X-CEL: A Method to Estimate Near-Memory Acceleration Potential in Tile-Based MPSoCs. - Rheindt, Sven; Fried, Andreas; Lenke, Oliver; Nolte, Lars; Sabirov, Temur; Twardzik, Tim; Wild, Thomas; Herkersdorf, Andreas (2020)

Emergent Control of MPSoC Operation by a Hierarchical Supervisor / Reinforcement Learning Approach. - Maurer, Florian; Donyanavard, Bryan; Rahmani, Amir M.; Dutt, Nikil D.; Herkersdorf, Andreas (2020)

On-Chip Democracy: A Study on the Use of Voting Systems for Computer Cache Memory Management. - Doan, Nguyen Anh Vu; Srivatsa, Akshay; Fasfous, Nael; Nagel, Sebastian; Wild, Thomas; Herkersdorf, Andreas (2020)

X-Centric: A Survey on Compute-, Memory- and Application-Centric Computer Architectures. - Rheindt, Sven; Sabirov, Temur; Lenke, Oliver; Wild, Thomas; Herkersdorf, Andreas (2020)

Exploring Task and Channel Mapping Strategies in Fail-Operational and Hard Real-Time NoCs. - Koenen, Max; Doan, Nguyen Anh Vu; Wild, Thomas; Herkersdorf, Andreas (2020)

HyVE: A Hybrid Voting-based Eviction Policy for Caches. - Srivatsa, Akshay; Nagel, Sebastian; Fasfous, Nael; Doan, Nguyen Anh Vu; Wild, Thomas; Herkersdorf, Andreas (2020)

Inter-Server RSS: Extending Receive Side Scaling for Inter-Server Workload Distribution. - Oeldemann, Andreas; Biersack, Franz; Wild, Thomas; Herkersdorf, Andreas (2020)

Fine-Grained Power Modeling of Multicore Processors Using FFNNs. - Sagi, Mark; Doan, Nguyen Anh Vu; Fasfous, Nael; Wild, Thomas; Herkersdorf, Andreas (2020)

AXES: Approximation Manager for Emerging Memory Architectures. - Maity, Biswadip; Donyanavard, Bryan; Surhonne, Anmol; Rahmani, Amir M.; Herkersdorf, Andreas; Dutt, Nikil D. (CoRR, 2020)

Cryptographic Hashing in P4 Data Planes. - Scholz, Dominik; Oeldemann, Andreas; Geyer, Fabien; Gallenmüller, Sebastian; Stubbe, Henning; Wild, Thomas; Herkersdorf, Andreas; Carle, Georg (2019)

A Hybrid NoC Enabling Fail-Operational and Hard Real-Time Communication in MPSoC. - Koenen, Max; Doan, Nguyen Anh Vu; Wild, Thomas; Herkersdorf, Andreas (2019)

Network Coding in Networks-on-Chip with Lossy Links. - Vonbun, Michael; Doan, Nguyen Anh Vu; Wild, Thomas; Herkersdorf, Andreas (2019)

The information processing factory: a paradigm for life cycle management of dependable systems. - Rambo, Eberle A.; Kadeed, Thawra; Ernst, Rolf; Seo, Minjun; Kurdahi, Fadi J.; Donyanavard, Bryan; Melo, Caio Batista de; Maity, Biswadip; Moazzemi, Kasra; Stewart, Kenneth Michael; Yi, Saehanseul; Rahmani, Amir M.; et al. (2019)

Multi-Objective Optimization of Channel Mapping for Fail-Operational Hybrid TDM NoCs. - Doan, Nguyen Anh Vu; Koenen, Max; Wild, Thomas; Herkersdorf, Andreas (2019)

Multicore Power Estimation using Independent Component Analysis Based Modeling. - Sagi, Mark; Doan, Nguyen Anh Vu; Wild, Thomas; Herkersdorf, Andreas (2019)

NEMESYS: near-memory graph copy enhanced system-software. - Rheindt, Sven; Fried, Andreas; Lenke, Oliver; Nolte, Lars; Wild, Thomas; Herkersdorf, Andreas (2019)

SOSA: Self-Optimizing Learning with Self-Adaptive Control for Hierarchical System-on-Chip Management. - Donyanavard, Bryan; Mück, Tiago; Rahmani, Amir M.; Dutt, Nikil D.; Sadighi, Armin; Maurer, Florian; Herkersdorf, Andreas (2019)

APEC: improved acknowledgement prioritization through erasure coding in bufferless NoCs. - Vonbun, Michael; Schiechel, Adrian; Doan, Nguyen Anh Vu; Wild, Thomas; Herkersdorf, Andreas (2019)

Channel mapping strategies for effective protection switching in fail-operational hard real-time NoCs. - Koenen, Max; Doan, Nguyen Anh Vu; Wild, Thomas; Herkersdorf, Andreas (2019)

CoD: Coherence-on-Demand - Runtime Adaptable Working Set Coherence for DSM-Based Manycore Architectures. - Srivatsa, Akshay; Rheindt, Sven; Gabriel, Dirk; Wild, Thomas; Herkersdorf, Andreas (2019)

SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore Architectures. - Rheindt, Sven; Maier, Sebastian; Schmaus, Florian; Wild, Thomas; Schröder-Preikschat, Wolfgang; Herkersdorf, Andreas (2019)

Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications. - Goldbrunner, Thomas; Doan, Nguyen Anh Vu; Poças, Diogo; Wild, Thomas; Herkersdorf, Andreas (2019)

The Information Processing Factory: Organization, Terminology, and Definitions. - Rambo, Eberle A.; Donyanavard, Bryan; Seo, Minjun; Maurer, Florian; Kadeed, Thawra; Melo, Caio Batista de; Maity, Biswadip; Surhonne, Anmol; Herkersdorf, Andreas; Kurdahi, Fadi J.; Dutt, Nikil D.; Ernst, Rolf (CoRR, 2019)

Platform-Centric Self-Awareness as a Key Enabler for Controlling Changes in CPS. - Möstl, Mischa; Schlatow, Johannes; Ernst, Rolf; Dutt, Nikil D.; Nassar, Ahmed; Rahmani, Amir-Mohammad; Kurdahi, Fadi J.; Wild, Thomas; Sadighi, Armin; Herkersdorf, Andreas (Proc. IEEE, 2018)

CaCAO: Complex and Compositional Atomic Operations for NoC-Based Manycore Platforms. - Rheindt, Sven; Schenk, Andreas; Srivatsa, Akshay; Wild, Thomas; Herkersdorf, Andreas (2018)

BiSME: A Hardware Coprocessor to Perform Signature Matching at Multi-Gigabit Rates. - Shankar, Subramanian Shiva; Lin, Pinxing; Herkersdorf, Andreas; Wild, Thomas (2018)

Design methodologies for enabling self-awareness in autonomous systems. - Sadighi, Armin; Donyanavard, Bryan; Kadeed, Thawra; Moazzemi, Kasra; Mück, Tiago; Nassar, Ahmed; Rahmani, Amir M.; Wild, Thomas; Dutt, Nikil D.; Ernst, Rolf; Herkersdorf, Andreas; Kurdahi, Fadi J. (2018)

FlueNT10G: A Programmable FPGA-based Network Tester for Multi-10-Gigabit Ethernet. - Oeldemann, Andreas; Wild, Thomas; Herkersdorf, Andreas (2018)

In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures. - Masing, Leonard; Srivatsa, Akshay; Kreß, Fabian; Anantharajaiah, Nidhi; Herkersdorf, Andreas; Becker, Jürgen (2018)

Memory Access Pattern Profiling for Streaming Applications Based on MATLAB Models. - Goldbrunner, Thomas; Wild, Thomas; Herkersdorf, Andreas (2018)

DiaSys: Improving SoC insight through on-chip diagnosis. - Wagner, Philipp; Wild, Thomas; Herkersdorf, Andreas (J. Syst. Archit., 2017)

Efficient task spawning for shared memory and message passing in many-core architectures. - Zaib, Aurang; Wild, Thomas; Herkersdorf, Andreas; Heisswolf, Jan; Becker, Jürgen; Weichslgartner, Andreas; Teich, Jürgen (J. Syst. Archit., 2017)

Reducing Data Center Resource Over-Provisioning Through Dynamic Load Management for Virtualized Network Functions. - Oeldemann, Andreas; Wild, Thomas; Herkersdorf, Andreas (2017)

A non-intrusive, operating system independent spinlock profiler for embedded multicore systems. - Li, Lin; Wagner, Philipp; Mayer, Albrecht; Wild, Thomas; Herkersdorf, Andreas (2017)

Self-awareness in autonomous automotive systems. - Schlatow, Johannes; Möstl, Mischa; Ernst, Rolf; Nolte, Marcus; Jatzkowski, Inga; Maurer, Markus; Herber, Christian; Herkersdorf, Andreas (2017)

Adaptive Reliability for Fault Tolerant Multicore Systems. - Alouani, Ihsen; Wild, Thomas; Herkersdorf, Andreas; Niar, Smaïl (2017)

A Divide and Conquer State Grouping Method for Bitmap Based Transition Compression. - Shankar, Subramanian Shiva; Lin, Pinxing; Herkersdorf, Andreas; Wild, Thomas (2017)

Region based cache coherence for tiled MPSoCs. - Srivatsa, Akshay; Rheindt, Sven; Wild, Thomas; Herkersdorf, Andreas (2017)

Dark silicon management: an integrated and coordinated cross-layer approach. - Pagani, Santiago; Bauer, Lars; Chen, Qingqing; Glocker, Elisabeth; Hannig, Frank; Herkersdorf, Andreas; Khdr, Heba; Pathania, Anuj; Schlichtmann, Ulf; Schmitt-Landsiedel, Doris; Sagi, Mark; Sousa, Éricles; et al. (it Inf. Technol., 2016)

ANN Predicted Apps-Usage Aware Linux Scheduler for Asymmetrical Multi Cluster SoC. - Rex, Hou Zhao Qi; Chuen, Jong Ching; Herkersdorf, Andreas (J. Softw., 2016)

MPSoC application resilience by hardware-assisted communication virtualization. - Rosch, Stefan; Rauchfuss, Holm; Wallentowitz, Stefan; Wild, Thomas; Herkersdorf, Andreas (Microelectron. Reliab., 2016)

DiaSys: On-Chip Trace Analysis for Multi-processor System-on-Chip. - Wagner, Philipp; Wild, Thomas; Herkersdorf, Andreas (2016)

Estimation of End-to-End Packet Error Rates for NoC Multicasts. - Vonbun, Michael; Wild, Thomas; Herkersdorf, Andreas (2016)

Disaggregated FPGAs: Network Performance Comparison against Bare-Metal Servers, Virtual Machines and Linux Containers. - Weerasinghe, Jagath; Abel, François; Hagleitner, Christoph; Herkersdorf, Andreas (2016)

Conquering MPSoC complexity with principles of a self-aware information processing factory. - Dutt, Nikil D.; Kurdahi, Fadi J.; Ernst, Rolf; Herkersdorf, Andreas (2016)

Resolving Performance Interference in SR-IOV Setups with PCIe Quality-of-Service Extensions. - Richter, Andre Oliver; Herber, Christian; Wild, Thomas; Herkersdorf, Andreas (2016)

Linux apps-usage-driven power dissipation-aware scheduler. - Rex, Hou Zhao Qi; Chuen, Jong Ching; Herkersdorf, Andreas (2016)

What happens on an MPSoC stays on an MPSoC - unfortunately! - Wagner, Philipp; Li, Lin; Wild, Thomas; Mayer, Albrecht; Herkersdorf, Andreas (2016)

Hardware acceleration of signature matching through multi-layer transition bit masking. - Shankar, Subramanian Shiva; Lin, Pinxing; Herkersdorf, Andreas; Wild, Thomas (2016)

A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems. - Li, Lin; Wagner, Philipp; Ramaswamy, Ramesh; Mayer, Albrecht; Wild, Thomas; Herkersdorf, Andreas (2016)

TCU: A Multi-Objective Hardware Thread Mapping Unit for HPC Clusters. - Pujari, Ravi Kumar; Wild, Thomas; Herkersdorf, Andreas (2016)

Improving SoC Insight Through On-Chip Diagnosis. - Wagner, Philipp; Wild, Thomas; Herkersdorf, Andreas (CoRR, 2016)

Adaptive multi-layer techniques for increased system dependability. - Bauer, Lars; Henkel, Jörg; Herkersdorf, Andreas; Kochte, Michael A.; Kühn, Johannes Maximilian; Rosenstiel, Wolfgang; Schweizer, Thomas; Wallentowitz, Stefan; Wenzel, Volker; Wild, Thomas; Wunderlich, Hans-Joachim; Zhang, Hongyan (it Inf. Technol., 2015)

Denial-of-Service attacks on PCI passthrough devices: Demonstrating the impact on network- and storage-I/O performance. - Richter, Andre Oliver; Herber, Christian; Wild, Thomas; Herkersdorf, Andreas (J. Syst. Archit., 2015)

Introduction to the Special Issue on Testing, prototyping, and debugging of multi-core architectures. - Hannig, Frank; Herkersdorf, Andreas (J. Syst. Archit., 2015)

A Hardware/Software Approach for Mitigating Performance Interference Effects in Virtualized Environments Using SR-IOV. - Richter, Andre Oliver; Herber, Christian; Wallentowitz, Stefan; Wild, Thomas; Herkersdorf, Andreas (2015)

Fault-tolerant communication in invasive networks on chip. - Heisswolf, Jan; Weichslgartner, Andreas; Zaib, Aurang; Friederich, Stephanie; Masing, Leonard; Stein, Carsten; Duden, Marco; Klopfer, Roman; Teich, Jürgen; Wild, Thomas; Herkersdorf, Andreas; Becker, Jürgen (2015)

SgInt: Safeguarding Interrupts for Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using Non Transparent Bridges. - Münch, Daniel; Paulitsch, Michael; Hanka, Oliver; Herkersdorf, Andreas (2015)

Network Interface with Task Spawning Support for NoC-Based DSM Architectures. - Zaib, Aurang; Heißwolf, Jan; Weichslgartner, Andreas; Wild, Thomas; Teich, Jürgen; Becker, Jürgen; Herkersdorf, Andreas (2015)

Real-time capable CAN to AVB ethernet gateway using frame aggregation and scheduling. - Herber, Christian; Richter, Andre Oliver; Wild, Thomas; Herkersdorf, Andreas (2015)

MPIOV: scaling hardware-based I/O virtualization for mixed-criticality embedded real-time systems using non transparent bridges to (multi-core) multi-processor systems. - Münch, Daniel; Paulitsch, Michael; Hanka, Oliver; Herkersdorf, Andreas (2015)

An Analytic Approach on End-to-End Packet Error Rate Estimation for Network-on-Chip. - Vonbun, Michael; Wallentowitz, Stefan; Oeldemann, Andreas; Herkersdorf, Andreas (2015)

IOMPU: Spatial Separation for Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using Non-transparent Bridges. - Münch, Daniel; Paulitsch, Michael; Herkersdorf, Andreas (2015)

Design and Evaluation of a Low-Latency AVB Ethernet Endpoint Based on ARM SoC. - Herber, Christian; Saeed, Ammar; Herkersdorf, Andreas (2015)

A hardware-based multi-objective thread mapper for tiled manycore architectures. - Pujari, Ravi Kumar; Wild, Thomas; Herkersdorf, Andreas (2015)

Monitoring of I/O for safety-critical systems using PCI express advanced error reporting. - Münch, Daniel; Paulitsch, Michael; Herkersdorf, Andreas (2015)

Fail-operational in safety-related automotive multi-core systems. - Kohn, André; Kasmeyer, Michael; Schneider, Rolf; Roger, Andre; Stellwag, Claus; Herkersdorf, Andreas (2015)

Sharer status-based caching in tiled multiprocessor systems-on-chip. - Damodaran, P. Parayil Mana; Zaib, Aurang; Wallentowitz, Stefan; Wild, Thomas; Herkersdorf, Andreas (2015)

Enabling FPGAs in Hyperscale Data Centers. - Weerasinghe, Jagath; Abel, François; Hagleitner, Christoph; Herkersdorf, Andreas (2015)

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience. - Herkersdorf, Andreas; Aliee, Hananeh; Engel, Michael; Glaß, Michael; Gimmler-Dumont, Christina; Henkel, Jörg; Kleeberger, Veit; Kochte, Michael A.; Kühn, Johannes Maximilian; Mueller-Gritschneder, Daniel; Nassif, Sani R.; Rauchfuss, Holm; et al. (Microelectron. Reliab., 2014)

Spatial and temporal isolation of virtual CAN controllers. - Herber, Christian; Richter, Andre Oliver; Rauchfuss, Holm; Herkersdorf, Andreas (SIGBED Rev., 2014)

The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. - Heisswolf, Jan; Zaib, Aurang; Weichslgartner, Andreas; Karle, Martin; Singh, Maximilian; Wild, Thomas; Teich, Jürgen; Herkersdorf, Andreas; Becker, Jürgen (2014)

Temporal Separation for Hardware-Based I/O Virtualization for Mixed-Criticality Embedded Real-Time Systems Using PCIe SR-IOV. - Münch, Daniel; Paulitsch, Michael; Herkersdorf, Andreas (2014)

Performance Isolation Exposure in Virtualized Platforms with PCI Passthrough I/O Sharing. - Richter, Andre Oliver; Herber, Christian; Rauchfuss, Holm; Wild, Thomas; Herkersdorf, Andreas (2014)

CAP: Communication Aware Programming. - Heisswolf, Jan; Zaib, Aurang; Zwinkau, Andreas; Kobbe, Sebastian; Weichslgartner, Andreas; Teich, Jürgen; Henkel, Jörg; Snelting, Gregor; Herkersdorf, Andreas; Becker, Jürgen (2014)

Distributed cooperative shared last-level caching in tiled multiprocessor system on chip. - Damodaran, Preethi P.; Wallentowitz, Stefan; Herkersdorf, Andreas (2014)

System integration - The bridge between More than Moore and More Moore. - Heinig, Andy; Dietrich, Manfred; Herkersdorf, Andreas; Miller, Felix; Wild, Thomas; Hahn, Kai; Grünewald, Armin; Brück, Rainer; Krohnert, Steffen; Reisinger, Jochen (2014)

Hardware virtualization support for shared resources in mixed-criticality multicore systems. - Sander, Oliver; Sandmann, Timo; Duy, Viet Vu; Bähr, Steffen; Bapp, Falco; Becker, Jürgen; Michel, Hans-Ulrich; Kaule, Dirk; Adam, Daniel; Lübbers, Enno; Hairbucher, Jürgen; Richter, Andre Oliver; et al. (2014)

Connecting different worlds - Technology abstraction for reliability-aware design and Test. - Schlichtmann, Ulf; Kleeberger, Veit; Abraham, Jacob A.; Evans, Adrian; Gimmler-Dumont, Christina; Glaß, Michael; Herkersdorf, Andreas; Nassif, Sani R.; Wehn, Norbert (2014)

Iterative FPGA Implementation Easing Safety Certification for Mixed-Criticality Embedded Real-Time Systems. - Münch, Daniel; Paulitsch, Michael; Honold, Michael; Schlecker, Wolfgang; Herkersdorf, Andreas (2014)

Dependable task and communication migration in tiled manycore system-on-chip. - Wallentowitz, Stefan; Rosch, Stefan; Wild, Thomas; Herkersdorf, Andreas; Wenzel, Volker; Henkel, Jörg (2014)

Deadline-Aware Interrupt Coalescing in Controller Area Network (CAN). - Herber, Christian; Richter, Andre Oliver; Wild, Thomas; Herkersdorf, Andreas (2014)

Apps-usage driven energy management for multicore mobile computing systems. - Rex, Hou Zhao Qi; Chuen, Jong Ching; Herkersdorf, Andreas (2014)

Deep packet inspection in residential gateways and routers: Issues and challenges. - Shankar, Subramanian Shiva; Lin, Pinxing; Herkersdorf, Andreas (2014)

A network virtualization approach for performance isolation in controller area network (CAN). - Herber, Christian; Richter, Andre Oliver; Wild, Thomas; Herkersdorf, Andreas (2014)

An automotive specific MILP model targeting power-aware function partitioning. - Walla, Gregor; Herkersdorf, Andreas; Enger, Andre S.; Barthels, Andreas; Michel, Hans-Ulrich (2014)

A Layered Modeling and Simulation Approach to investigate Resource-aware Computing in MPSoCs. - Zaib, Aurang; Raju, Prashanth; Wild, Thomas; Herkersdorf, Andreas (CoRR, 2014)

Virtualized and fault-tolerant inter-layer-links for 3D-ICs. - Miller, Felix; Wild, Thomas; Herkersdorf, Andreas (Microprocess. Microsystems, 2013)

A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience. - Kleeberger, Veit; Gimmler-Dumont, Christina; Weis, Christian; Herkersdorf, Andreas; Mueller-Gritschneder, Daniel; Nassif, Sani R.; Schlichtmann, Ulf; Wehn, Norbert (IEEE Micro, 2013)

Introduction to the special section on multiprocessor system-on-chip for cyber-physical systems. - Hübner, Michael; Herkersdorf, Andreas (ACM Trans. Embed. Comput. Syst., 2013)

Virtual networks - distributed communication resource management. - Heisswolf, Jan; Zaib, Aurang; Weichslgartner, Andreas; König, Ralf; Wild, Thomas; Teich, Jürgen; Herkersdorf, Andreas; Becker, Jürgen (ACM Trans. Reconfigurable Technol. Syst., 2013)

Self-virtualized CAN Controller for Multi-core Processors in Real-Time Applications. - Herber, Christian; Richter, Andre Oliver; Rauchfuss, Holm; Herkersdorf, Andreas (2013)

HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation. - Wallentowitz, Stefan; Wild, Thomas; Herkersdorf, Andreas (2013)

Hardware-Based I/O Virtualization for Mixed Criticality Real-Time Systems Using PCIe SR-IOV. - Münch, Daniel; Isfort, Ole; Mueller, Kevin; Paulitsch, Michael; Herkersdorf, Andreas (2013)

AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. - Zaib, Aurang; Heisswolf, Jan; Weichslgartner, Andreas; Wild, Thomas; Teich, Jürgen; Becker, Jürgen; Herkersdorf, Andreas (2013)

A Design Space Exploration Framework For Automotive Embedded Systems And Their Power Management. - Walla, Gregor; Molotnikov, Zaur; Michel, Hans-Ulrich; Stechele, Walter; Barthels, Andreas; Herkersdorf, Andreas (2013)

Potentials and Challenges for Multi-Core Processors in Robotic Applications. - Herkersdorf, Andreas; Paul, Johny; Pujari, Ravi Kumar; Stechele, Walter; Wallentowitz, Stefan; Wild, Thomas; Zaib, Aurang (2013)

Hardware Supported Adaptive Data Collection for Networks on Chip. - Heisswolf, Jan; Weichslgartner, Andreas; Zaib, Aurang; König, Ralf; Wild, Thomas; Herkersdorf, Andreas; Teich, Jürgen; Becker, Jürgen (2013)

Evaluation of hop count advantages of network-coded 2D-mesh NoCs. - Vonbun, Michael; Wallentowitz, Stefan; Feilen, Michael; Stechele, Walter; Herkersdorf, Andreas (2013)

Open Tiled Manycore System-on-Chip - Wallentowitz, Stefan; Wagner, Philipp; Tempelmeier, Michael; Wild, Thomas; Herkersdorf, Andreas (CoRR, 2013)

Invasive Computing - Common Terms and Granularity of Invasion - Teich, Jürgen; Schröder-Preikschat, Wolfgang; Herkersdorf, Andreas (CoRR, 2013)

Multicore Enablement for Embedded and Cyber Physical Systems (Dagstuhl Seminar 13052). - Herkersdorf, Andreas; Paulitsch, Michael (Dagstuhl Reports, 2013)

Multicore Enablement for Automotive Cyber Physical Systems. - Herkersdorf, Andreas; Michel, Hans-Ulrich; Rauchfuss, Holm; Wild, Thomas (it Inf. Technol., 2012)

Benefits of selective packet discard in networks-on-chip. - Lankes, Andreas; Wild, Thomas; Wallentowitz, Stefan; Herkersdorf, Andreas (ACM Trans. Archit. Code Optim., 2012)

Enhanced Reliability in Tiled Manycore Architectures through Transparent Task Relocation. - Rauchfuss, Holm; Wild, Thomas; Herkersdorf, Andreas (2012)

Invasive manycore architectures. - Henkel, Jörg; Herkersdorf, Andreas; Bauer, Lars; Wild, Thomas; Hübner, Michael; Pujari, Ravi Kumar; Grudnitsky, Artjom; Heisswolf, Jan; Zaib, Aurang; Vogel, Benjamin; Lari, Vahid; Kobbe, Sebastian (2012)

A Real-Time Capable Virtualized Information and Communication Technology Infrastructure for Automotive Systems. - Drössler, Sebastian; Eichhorn, Michael; Holzknecht, S.; Müller-Rathgeber, Bernd; Rauchfuss, Holm; Zwick, Michael; Biebl, Erwin M.; Diepold, Klaus; Eberspächer, Jörg; Herkersdorf, Andreas; Stechele, Walter; Steinbach, Eckehard G.; et al. (2012)

Virtual platforms: Breaking new grounds. - Leupers, Rainer; Martin, Grant; Plyaskin, Roman; Herkersdorf, Andreas; Schirrmeister, Frank; Kogel, Tim; Vaupel, Martin (2012)

A low-overhead monitoring ring interconnect for MPSoC parameter optimization. - Bouajila, Abdelmajid; Lakhtel, Abdallah; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas (2012)

TSV-virtualization for Multi-protocol-Interconnect in 3D-ICs. - Miller, Felix; Wild, Thomas; Herkersdorf, Andreas (2012)

Analytical Design Space Exploration Based on Statistically Refined Runtime and Logic Estimation for Software Defined Radios. - Ihmig, Matthias; Feilen, Michael; Herkersdorf, Andreas (2012)

Dependable embedded systems: The German research foundation DFG priority program SPP 1500. - Henkel, Jörg; Bringmann, Oliver; Herkersdorf, Andreas; Rosenstiel, Wolfgang; Wehn, Norbert (2012)

An integrated simulation framework for invasive computing. - Gerndt, Michael; Hannig, Frank; Herkersdorf, Andreas; Hollmann, Andreas; Meyer, Marcel; Roloff, Sascha; Weidendorfer, Josef; Wild, Thomas; Zaib, Aurang (2012)

A framework for Open Tiled Manycore System-On-Chip. - Wallentowitz, Stefan; Lankes, Andreas; Zaib, Aurang; Wild, Thomas; Herkersdorf, Andreas (2012)

Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. - Heisswolf, Jan; Zaib, Aurang; Weichslgartner, Andreas; König, Ralf; Wild, Thomas; Teich, Jürgen; Herkersdorf, Andreas; Becker, Jürgen (2012)

System-level software performance simulation considering out-of-order processor execution. - Plyaskin, Roman; Wild, Thomas; Herkersdorf, Andreas (2012)

Multicore enablement for Cyber Physical Systems. - Herkersdorf, Andreas (2012)

Architecture of Computing Systems - ARCS 2012 - 25th International Conference, Munich, Germany, February 28 - March 2, 2012. Proceedings (Springer, 2012)

ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany (GI, 2012)

Advanced Packet Segmentation and Buffering Algorithms in Network Processors. - Llorente, Daniel; Karras, Kimon; Wild, Thomas; Herkersdorf, Andreas (Trans. High Perform. Embed. Archit. Compil., 2011)

Design and architectures for dependable embedded systems. - Henkel, Jörg; Bauer, Lars; Becker, Joachim; Bringmann, Oliver; Brinkschulte, Uwe; Chakraborty, Samarjit; Engel, Michael; Ernst, Rolf; Härtig, Hermann; Hedrich, Lars; Herkersdorf, Andreas; Kapitza, Rüdiger; et al. (2011)

An approach to improve accuracy of source-level TLMs of embedded software. - Wang, Zhonglei; Lu, Kun; Herkersdorf, Andreas (2011)

An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. - Bouajila, Abdelmajid; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas (2011)

Applying autonomic principles for workload management in multi-core systems on chip. - Zeppenfeld, Johannes; Herkersdorf, Andreas (2011)

Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores. - Ebi, Thomas; Rauchfuss, Holm; Herkersdorf, Andreas; Henkel, Jörg (2011)

Accelerating collective communication in message passing on manycore System-on-Chip. - Wallentowitz, Stefan; Meyer, Marcel; Wild, Thomas; Herkersdorf, Andreas (2011)

Context-aware compiled simulation of out-of-order processor behavior based on atomic traces. - Plyaskin, Roman; Herkersdorf, Andreas (2011)

Combining Software and Hardware LCS for Lightweight On-chip Learning. - Bernauer, Andreas; Zeppenfeld, Johannes; Bringmann, Oliver; Herkersdorf, Andreas; Rosenstiel, Wolfgang (2011)

Autonomic System on Chip Platform. - Bouajila, Abdelmajid; Zeppenfeld, Johannes; Stechele, Walter; Bernauer, Andreas; Bringmann, Oliver; Rosenstiel, Wolfgang; Herkersdorf, Andreas (2011)

Applying ASoC to Multi-core Applications for Workload Management. - Zeppenfeld, Johannes; Bouajila, Abdelmajid; Stechele, Walter; Bernauer, Andreas; Bringmann, Oliver; Rosenstiel, Wolfgang; Herkersdorf, Andreas (2011)

Hardware Support for Efficient Resource Utilization in Manycore Processor Systems. - Herkersdorf, Andreas; Lankes, Andreas; Meitinger, Michael; Ohlendorf, Rainer; Wallentowitz, Stefan; Wild, Thomas; Zeppenfeld, Johannes (2011)

Invasive Computing: An Overview. - Teich, Jürgen; Henkel, Jörg; Herkersdorf, Andreas; Schmitt-Landsiedel, Doris; Schröder-Preikschat, Wolfgang; Snelting, Gregor (2011)

Organic Computing - Design of Self-Organizing Systems (Dagstuhl Seminar 11181). - Bellman, Kirstie L.; Herkersdorf, Andreas; Hinchey, Michael G. (Dagstuhl Reports, 2011)

Software performance simulation strategies for high-level embedded system design. - Wang, Zhonglei; Herkersdorf, Andreas (Perform. Evaluation, 2010)

A folded pipeline network processor architecture for 100 Gbit/s networks. - Karras, Kimon; Wild, Thomas; Herkersdorf, Andreas (2010)

Autonomic Workload Management for Multi-core Processor Systems. - Zeppenfeld, Johannes; Herkersdorf, Andreas (2010)

A Method for Accurate High-Level Performance Evaluation of MPSoC Architectures Using Fine-Grained Generated Traces. - Plyaskin, Roman; Herkersdorf, Andreas (2010)

A rapid prototyping system for error-resilient multi-processor systems-on-chip. - May, Matthias; Wehn, Norbert; Bouajila, Abdelmajid; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas; Ziener, Daniel; Teich, Jürgen (2010)

Architectural Vulnerability Factor Estimation with Backwards Analysis. - Hartl, Robert; Rohatschek, Andreas J.; Stechele, Walter; Herkersdorf, Andreas (2010)

An Application-Aware Load Balancing Strategy for Network Processors. - Ohlendorf, Rainer; Meitinger, Michael; Wild, Thomas; Herkersdorf, Andreas (2010)

Combining Software and Hardware LCS for Lightweight On-Chip Learning. - Bernauer, Andreas; Zeppenfeld, Johannes; Bringmann, Oliver; Herkersdorf, Andreas; Rosenstiel, Wolfgang (2010)

Towards Scalability and Reliability of Autonomic Systems on Chip. - Zeppenfeld, Johannes; Bouajila, Abdelmajid; Herkersdorf, Andreas; Stechele, Walter (2010)

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks. - Lankes, Andreas; Wild, Thomas; Herkersdorf, Andreas; Sonntag, Sören; Reinig, Helmut (2010)

High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations. - Plyaskin, Roman; Masrur, Alejandro; Geier, Martin; Chakraborty, Samarjit; Herkersdorf, Andreas (2010)

FlexPath NP - Flexible, Dynamically Reconfigurable Processing Paths in Network Processors. - Ohlendorf, Rainer; Meitinger, Michael; Wild, Thomas; Herkersdorf, Andreas (2010)

SysCOLA: a framework for co-development of automotive software and system platform. - Wang, Zhonglei; Herkersdorf, Andreas; Haberl, Wolfgang; Wechs, Martin (2009)

An efficient approach for system-level timing simulation of compiler-optimized embedded software. - Wang, Zhonglei; Herkersdorf, Andreas (2009)

An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs. - Traboulsi, Shadi; Meitinger, Michael; Ohlendorf, Rainer; Herkersdorf, Andreas (2009)

Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources. - Lankes, Andreas; Wild, Thomas; Herkersdorf, Andreas (2009)

NoC topology exploration for mobile multimedia applications. - Lankes, Andreas; Herkersdorf, Andreas; Sonntag, Sören; Reinig, Helmut (2009)

Flow Analysis on Intermediate Source Code for WCET Estimation of Compiler-Optimized Programs. - Wang, Zhonglei; Herkersdorf, Andreas (2009)

A Processing Path Dispatcher in Network Processor MPSoCs. - Ohlendorf, Rainer; Meitinger, Michael; Wild, Thomas; Herkersdorf, Andreas (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A Hardware Packet Re-Sequencer Unit for Network Processors. - Meitinger, Michael; Ohlendorf, Rainer; Wild, Thomas; Herkersdorf, Andreas (2008)

Buffer allocation for advanced packet segmentation in Network Processors. - Llorente, Daniel; Karras, Kimon; Wild, Thomas; Herkersdorf, Andreas (2008)

Determining the Fidelity of Hardware-In-the-Loop Simulation Coupling Systems. - Köhler, Christian; Mayer, Albrecht; Herkersdorf, Andreas (2008)

Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. - Becker, Jürgen; Hübner, Michael; Esser, Robert; Herkersdorf, Andreas; Stechele, Walter; Lauer, Vera (2008)

A Model Driven Development Approach for Implementing Reactive Systems in Hardware. - Wang, Zhonglei; Herkersdorf, Andreas; Merenda, Stefano; Tautschnig, Michael (2008)

Fine grain reconfigurable architectures. - Angermeier, Josef; Majer, Mateusz; Teich, Jürgen; Braun, Lars; Schwalb, Tobias; Graf, Philipp; Hübner, Michael; Becker, Jürgen; Lübbers, Enno; Platzner, Marco; Claus, Christopher; Stechele, Walter; et al. (2008)

Network processors. - Pionteck, Thilo; Koch, Roman; Albrecht, Carsten; Maehle, Erik; Meitinger, Michael; Ohlendorf, Rainer; Wild, Thomas; Herkersdorf, Andreas (2008)

Workshop "Adaptive and Organic Systems". - Herkersdorf, Andreas; Stechele, Walter; Müller-Schloer, Christian; Schmeck, Hartmut (2008)

Learning Classifier Tables for Autonomic Systems on Chip. - Zeppenfeld, Johannes; Bouajila, Abdelmajid; Stechele, Walter; Herkersdorf, Andreas (2008)

A Simulation Approach for Performance Validation during Embedded Systems Design. - Wang, Zhonglei; Haberl, Wolfgang; Herkersdorf, Andreas; Wechs, Martin (2008)

FlexPath NP - A network processor architecture with flexible processing paths. - Meitinger, Michael; Ohlendorf, Rainer; Wild, Thomas; Herkersdorf, Andreas (2008)

Improving memory subsystem performance in network processors with smart packet segmentation. - Karras, Kimon; Llorente, Daniel; Wild, Thomas; Herkersdorf, Andreas (2008)

SciSim: a software performance estimation framework using source code instrumentation. - Wang, Zhonglei; Sánchez, Antonio; Herkersdorf, Andreas (2008)

Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision - Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme). - Claus, Christopher; Stechele, Walter; Herkersdorf, Andreas (it Inf. Technol., 2007)

Simulated and measured performance evaluation of RISC-based SoC platforms in network processing applications. - Ohlendorf, Rainer; Wild, Thomas; Meitinger, Michael; Rauchfuss, Holm; Herkersdorf, Andreas (J. Syst. Archit., 2007)

A Programmable Stream Processing Engine for Packet Manipulation in Network Processors. - Meitinger, Michael; Ohlendorf, Rainer; Wild, Thomas; Herkersdorf, Andreas (2007)

Performance evaluation for system-on-chip architectures using trace-based transaction level simulation. - Wild, Thomas; Herkersdorf, Andreas; Ohlendorf, Rainer (2006)

AutoVision: flexible processor architecture for video-assisted driving. - Herkersdorf, Andreas; Stechele, Walter (2006)

An Architecture for Runtime Evaluation of SoC Reliability. - Bernauer, Andreas; Bringmann, Oliver; Rosenstiel, Wolfgang; Bouajila, Abdelmajid; Stechele, Walter; Herkersdorf, Andreas (2006)

Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. - Bouajila, Abdelmajid; Bernauer, Andreas; Herkersdorf, Andreas; Rosenstiel, Wolfgang; Bringmann, Oliver; Stechele, Walter (2006)

Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications. - Ohlendorf, Rainer; Wild, Thomas; Meitinger, Michael; Rauchfuss, Holm; Herkersdorf, Andreas (2006)

Organic Computing at the System on Chip Level. - Bouajila, Abdelmajid; Zeppenfeld, Johannes; Stechele, Walter; Herkersdorf, Andreas; Bernauer, Andreas; Bringmann, Oliver; Rosenstiel, Wolfgang (2006)

Reconfigurable Processing Units vs. Reconfigurable Interconnects. - Herkersdorf, Andreas; Claus, Christopher; Meitinger, Michael; Ohlendorf, Rainer; Wild, Thomas (2006)

TAPES - Trace-based architecture performance evaluation with SystemC. - Wild, Thomas; Herkersdorf, Andreas; Lee, Gyoo-Yeong (Des. Autom. Embed. Syst., 2005)

Robust header compression (ROHC) in next-generation network processors. - Taylor, David E.; Herkersdorf, Andreas; Döring, Andreas C.; Dittmann, Gero (IEEE/ACM Trans. Netw., 2005)

Adaptable DSP Functions for Dynamically Reconfigurable Communication Systems. - Suleman, Faisal; Eilers, Dirk; Steckenbiller, Helmut; Herkersdorf, Andreas (2005)

Towards a Framework and a Design Methodology for Autonomous SoC. - Lipsa, Gabriel Mihai; Herkersdorf, Andreas; Rosenstiel, Wolfgang; Bringmann, Oliver; Stechele, Walter (2005)

FlexPath NP: a network processor concept with application-driven flexible processing paths. - Ohlendorf, Rainer; Herkersdorf, Andreas; Wild, Thomas (2005)

Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. - Zuber, Paul; Windschiegl, Armin; Otálora, Raúl Medina Beltrán de; Stechele, Walter; Herkersdorf, Andreas (2005)

Towards a Framework and a Design Methodology for Autonomic SoC. - Lipsa, Gabriel Mihai; Herkersdorf, Andreas; Rosenstiel, Wolfgang; Bringmann, Oliver; Stechele, Walter (2005)

Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing. - Stechele, Walter; Herrmann, Stephan; Herkersdorf, Andreas (2004)

A Comparison of Parallel Programming Models of Network Processors. - Albrecht, Carsten; Hagenau, Rainer; Maehle, Erik; Döring, Andreas C.; Herkersdorf, Andreas (2004)

Buffer Schemes for Runtime Reconfiguration of Function Variants in Communication Systems. - Eilers, Dirk; Steckenbiller, Helmut; Herkersdorf, Andreas (2004)

Towards a Framework and a Design Methodology for Autonomic Integrated Systems. - Herkersdorf, Andreas; Rosenstiel, Wolfgang (2004)

Design methodology for a modular service-driven network processor architecture. - Gabrani, Maria; Dittmann, Gero; Döring, Andreas C.; Herkersdorf, Andreas; Sagmeister, Patricia; Lunteren, Jan van (Comput. Networks, 2003)

Performance evaluation of network processor architectures: combining simulation with analytical estimation. - Chakraborty, Samarjit; Künzli, Simon; Thiele, Lothar; Herkersdorf, Andreas; Sagmeister, Patricia (Comput. Networks, 2003)

IBM PowerNP network processor: Hardware, software, and applications. - Allen, James R., Jr.; Bass, Brian M.; Basso, Claude; Boivie, Richard H.; Calvignac, Jean; Davis, Gordon T.; Freléchoux, Laurent; Heddes, Marco; Herkersdorf, Andreas; Kind, Andreas; Logan, Joe F.; Peyravian, Mohammad; et al. (IBM J. Res. Dev., 2003)

Early analysis tools for system-on-a-chip design. - Darringer, John A.; Bergamaschi, Reinaldo A.; Bhattacharya, Subhrajit; Brand, Daniel; Herkersdorf, Andreas; Morrell, Joseph K.; Nair, Indira; Sagmeister, Patricia; Shin, Youngsoo (IBM J. Res. Dev., 2002)

Technologies and building blocks for fast packet forwarding. - Bux, Werner; Denzel, Wolfgang E.; Engbersen, Ton; Herkersdorf, Andreas; Luijten, Ronald P. (IEEE Commun. Mag., 2001)

Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution. - Baechtold, Peter H.; Beakes, Michael P.; Buchmann, Peter; Clauberg, Rolf; Ewen, John F.; Gilsdorf, John F.; Hauviller, Philippe; Herkersdorf, Andreas; Garrec, Jean-Claude Le; Lemppenau, Wolfram W.; Parker, Ben; Pearson, Dale J.; et al. (IEEE J. Solid State Circuits, 2001)

Design Methodology for a Large Communication Chip. - Clauberg, Rolf; Buchmann, Peter; Herkersdorf, Andreas; Webb, David J. (IEEE Des. Test Comput., 2000)

A scalable modular architecture for SDH/SONET technology. - Clauberg, Rolf; Herkersdorf, Andreas; Lemppenau, Wolfram W.; Schindler, Hans R. (1999)

Route Discovery for Multistage Fabrics in ATM Switching Nodes. - Herkersdorf, Andreas; Heusler, L.; Maehle, Erik (Perform. Evaluation, 1995)

Route Discovery in Multistage Switch Fabrics. - Herkersdorf, Andreas; Heusler, L.; Maehle, Erik (1993)

Fast Connection Establishment in Large-Scale Networks. - Doeringer, Willibald A.; Dykeman, Douglas; Engbersen, Antonius P. J.; Guérin, Roch; Herkersdorf, Andreas; Heusler, L. (1993)

A method and a tool for the real-time evaluation of fast packet switching systems. - Herkersdorf, Andreas (Hartung-Gorre, 1991)