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ORCIDFrançois R. Boyer
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2020 – today
- 2021
[e1]François R. Boyer, Jean-Marc Seigneur, Mohamed-Amine Choukou, Redha Taïar:
AH 2021: 12th Augmented Human International Conference, Geneva, Switzerland. ACM 2021, ISBN 978-1-4503-9030-9 [contents]
2010 – 2019
- 2019
- [j4]Imad Benacer
, François-Raymond Boyer, Yvon Savaria:
A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking. IEEE Access 7: 2231-2243 (2019) - [j3]Imad Benacer, François-Raymond Boyer, Yvon Savaria:
HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices. IEEE Access 7: 130672-130684 (2019) - [c22]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design. FCCM 2019: 218-226 - [i3]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design. CoRR abs/1903.06693 (2019) - 2018
- [j2]Imad Benacer, François-Raymond Boyer, Yvon Savaria:
A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1939-1952 (2018) - [c21]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. FPGA 2018: 147-152 - [c20]Imad Benacer, François-Raymond Boyer, Yvon Savaria:
Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis. ISCAS 2018: 1-5 - [c19]Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois:
Extern Objects in P4: an ROHC Header Compression Scheme Case Study. NetSoft 2018: 517-522 - [c18]Imad Benacer, François-Raymond Boyer, Yvon Savaria:
HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches. NEWCAS 2018: 229-233 - 2017
- [c17]Imad Benacer, François-Raymond Boyer, Yvon Savaria:
A high-speed traffic manager architecture for flow-based networking. NEWCAS 2017: 161-164 - [i2]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. CoRR abs/1711.06613 (2017) - 2016
- [c16]Alexsandre B. Lacroix, J. M. Pierre Langlois, François-Raymond Boyer, Antoine Gosselin, Guy Bois:
Node configuration for the Aho-Corasick algorithm in Intrusion Detection Systems. ANCS 2016: 121-122 - [c15]Roya Alizadeh, Normand Bélanger, Yvon Savaria, François R. Boyer:
Performance characterization of an SCMA decoder. NEWCAS 2016: 1-4 - [c14]Imad Benacer, François-Raymond Boyer, Normand Bélanger, Yvon Savaria:
A fast systolic priority queue architecture for a flow-based Traffic Manager. NEWCAS 2016: 1-4 - [i1]Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois:
Extern Objects in P4: an ROHC Compression Case Study. CoRR abs/1611.05943 (2016) - 2013
- [c13]Marcel Siadjine Njinowa, Hung Tien Bui, François-Raymond Boyer:
Design of low power 4-bit flash ADC based on standard cells. NEWCAS 2013: 1-4 - 2010
- [c12]Marcel Siadjine Njinowa, Hung Tien Bui, François R. Boyer:
Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS). ISCAS 2010: 1312-1315
2000 – 2009
- 2009
- [c11]Abdelaziz Trabelsi, Mounir Boukadoum, François-Raymond Boyer:
Robust estimation of LP parameters in white noise with unknown variance. ICECS 2009: 335-338 - 2007
- [c10]Abdelaziz Trabelsi, François-Raymond Boyer, Yvon Savaria, Mounir Boukadoum:
Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis. ICECS 2007: 1364-1367 - [c9]Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria:
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. ISCAS 2007: 633-636 - 2006
- [c8]Bill Pontikakis, François R. Boyer, Yvon Savaria:
A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. ISCAS 2006 - 2005
- [c7]H. G. Epassa, François R. Boyer, Yvon Savaria:
Implementation of a cycle by cycle variable speed processor. ISCAS (4) 2005: 3335-3338 - [c6]Bill Pontikakis, François R. Boyer, Yvon Savaria:
Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. IWSOC 2005: 454-458 - 2004
- [c5]James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois:
.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation. DATE 2004: 732-733 - [c4]James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois:
ESys.Net: a new solution for embedded systems modeling and simulation. LCTES 2004: 107-114 - 2003
- [c3]Jérôme Chevalier, Mathieu Rondonneau, Olivier Benny, Guy Bois, El Mostapha Aboulhamid, François R. Boyer:
SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS. FDL 2003: 704-716 - 2001
- [j1]François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer:
Optimal design of synchronous circuits using software pipelining techniques. ACM Trans. Design Autom. Electr. Syst. 6(4): 516-532 (2001) - 2000
- [c2]François-Raymond Boyer, El Mostapha Aboulhamid, Yvon Savaria:
An efficient verification method for a class of multi-phase sequential circuits. ICECS 2000: 510-515
1990 – 1999
- 1998
- [c1]François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Imed Eddine Bennour:
Optimal design of synchronous circuits using software pipelining techniques. ICCD 1998: 62-67
Coauthor Index
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