Low Power Oriented CMOS Circuit Optimization Protocol - Verle, Alexandre; Michel, Xavier; Azémard, Nadine; Maurine, Philippe; Auvergne, Daniel (CoRR, 2007)

Logical effort model extension to propagation delay representation. - Lasbouygues, B.; Engels, Sylvain; Wilson, Robin; Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Low Power Oriented CMOS Circuit Optimization Protocol. - Verle, Alexandre; Michel, Xavier; Azémard, Nadine; Maurine, Philippe; Auvergne, Daniel (2005)

Delay bound based CMOS gate sizing technique. - Verle, Alexandre; Michel, Xavier; Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (2004)

Performance Metric Based Optimization Protocol. - Michel, Xavier; Verle, Alexandre; Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (2004)

Temperature Dependence in Low Power CMOS UDSM Process. - Lasbouygues, B.; Wilson, Robin; Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (2004)

Design Optimization with Automated Cell Generation. - Landrault, A.; Azémard, Nadine; Maurine, Philippe; Robert, Michel; Auvergne, Daniel (2004)

Physical Extension of the Logical Effort Model. - Lasbouygues, B.; Wilson, Robin; Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (2004)

Design Techniques for EEPROMs Embedded in Portable Systems on Chips. - Daga, Jean Michel; Papaix, Caroline; Merandat, Marc; Ricard, Stephane; Medulla, Giuseppe; Guichaoua, Jeanine; Auvergne, Daniel (IEEE Des. Test Comput., 2003)

Continuous representation of the performance of a CMOS library. - Lasbouygues, B.; Schindler, Joel; Engels, Sylvain; Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (2003)

CMOS Gate Sizing under Delay Constraint. - Verle, Alexandre; Michel, Xavier; Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (2003)

Metric Definition for Circuit Speed Optimization. - Michel, Xavier; Verle, Alexandre; Azémard, Nadine; Maurine, Philippe; Auvergne, Daniel (2003)

Transition time modeling in deep submicron CMOS. - Maurine, Philippe; Rezzoug, Mustapha; Azémard, Nadine; Auvergne, Daniel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Gate speed improvement at minimal power dissipation. - Maurine, Philippe; Michel, Xavier; Azémard, Nadine; Auvergne, Daniel (2002)

Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications. - Rahajandraibe, Wenceslas; Dufaza, Christian; Auvergne, Daniel; Cialdella, Bruno; Majoux, Bernard; Chowdhury, Vivek (2002)

Crosstalk Measurement Technique for CMOS ICs. - Picot, Fabrice; Coll, Philippe; Auvergne, Daniel (2002)

Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. - Landrault, Alexis; Pellier, Ludovic; Richard, Alexandre; Jay, Christian; Robert, Michel; Auvergne, Daniel (2002)

Structure Independent Representation of Output Transition Time for CMOS Library. - Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (2002)

POPS: A tool for delay/power performance optimization. - Azémard, Nadine; Auvergne, Daniel (J. Syst. Archit., 2001)

Gate Sizing for Low Power Design. - Maurine, Philippe; Azémard, Nadine; Auvergne, Daniel (2001)

Feasible Delay Bound Definition. - Azémard, Nadine; Aline, M.; Maurine, Philippe; Auvergne, Daniel (2001)

Output transition time modeling of CMOS structures. - Maurine, Philippe; Rezzoug, Mustapha; Auvergne, Daniel (2001)

Delay bound determination for timing closure satisfaction. - Azémard, Nadine; Aline, M.; Auvergne, Daniel (2001)

Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions. - Daga, Jean Michel; Papaix, Caroline; Merandat, Marc; Ricard, Stephane; Medulla, Giuseppe; Guichaoua, Jeanine; Auvergne, Daniel (2000)

Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. - Maurine, Philippe; Rezzoug, Mustapha; Auvergne, Daniel (2000)

Second Generation Delay Model for Submicron CMOS Process. - Rezzoug, Mustapha; Maurine, Philippe; Auvergne, Daniel (2000)

A comprehensive delay macro modeling for submicrometer CMOS logics. - Daga, Jean Michel; Auvergne, Daniel (IEEE J. Solid State Circuits, 1999)

Delay-power performance analysis. - Cremoux, S.; Aline, M.; Azémard, Nadine; Auvergne, Daniel (1999)

RF Interface Design Using Mixed-Mode Methodology. - Gallegos, Augusto; Silvestre, Philippe; Robert, Michel; Auvergne, Daniel (1999)

A Virtual CMOS Library Approach for East Layout Synthesis. - Moraes, Fernando; Robert, Michel; Auvergne, Daniel (1999)

A novel macromodel for power estimation in CMOS structures. - Turgis, S.; Auvergne, Daniel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Temperature Effect on Delay for Low Voltage Applications. - Daga, Jean Michel; Ottaviano, E.; Auvergne, Daniel (1998)

Internal power modelling and minimization in CMOS inverters. - Turgis, S.; Daga, Jean Michel; Portal, Josep M.; Auvergne, Daniel (1997)

Delay propagation effect in transistor gates. - Deschacht, Denis; Dabrin, Christophe; Auvergne, Daniel (IEEE J. Solid State Circuits, 1996)

Design and selection of buffers for minimum power-delay product. - Turgis, S.; Azémard, Nadine; Auvergne, Daniel (1996)

Delay modelling improvement for low voltage applications. - Daga, Jean Michel; Robert, Michel; Auvergne, Daniel (1995)

Explicit evaluation of short circuit power dissipation for CMOS logic structures. - Turgis, S.; Azémard, Nadine; Auvergne, Daniel (1995)

Influence of Locig Block Layout Architecture on FPGA Performance. - Robert, Michel; Torres, Lionel; Moraes, Fernando; Auvergne, Daniel (1994)

Post-layout timing simulation of CMOS circuits. - Deschacht, Denis; Robert, Michel; Azémard-Crestani, Nadine; Auvergne, Daniel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

P.SIZE: a sizing aid for optimized designs. - Azémard, Nadine; Bonzom, V.; Auvergne, Daniel (1992)

TVA: A timing verifier with analytic temporal modelling. - Navarro, D.; Roy, A.; Robert, Michel; Deschacht, Denis; Auvergne, Daniel (Microprocessing and Microprogramming, 1991)

Synchronous-mode evaluation of delays in CMOS structures. - Deschacht, Denis; Robert, Michel; Auvergne, Daniel (IEEE J. Solid State Circuits, 1991)

Formal sizing rules of CMOS circuits. - Auvergne, Daniel; Azémard, Nadine; Bonzom, V.; Deschacht, Denis; Robert, Michel (1991)

Input waveform slope effects in CMOS delays. - Auvergne, Daniel; Azémard, Nadine; Deschacht, Denis; Robert, Michel (IEEE J. Solid State Circuits, 1990)

Path runner: an accurate and fast timing analyser. - Deschacht, Denis; Pinede, P.; Robert, Michel; Auvergne, Daniel (1990)

FSPICE: a tool for fault modelling in MOS circuits. - Renovell, Michel; Cambon, Gaston; Auvergne, Daniel (Integr., 1985)