Low Power Oriented CMOS Circuit Optimization Protocol - Alexandre Verle; Xavier Michel; Nadine Azémard; Philippe Maurine; Daniel Auvergne (CoRR, 2007)

Logical effort model extension to propagation delay representation - B. Lasbouygues; Sylvain Engels; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Low Power Oriented CMOS Circuit Optimization Protocol - Alexandre Verle; Xavier Michel; Nadine Azémard; Philippe Maurine; Daniel Auvergne (2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, 2005)

Delay bound based CMOS gate sizing technique - Alexandre Verle; Xavier Michel; Philippe Maurine; Nadine Azémard; Daniel Auvergne (Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, 2004)

Performance Metric Based Optimization Protocol - Xavier Michel; Alexandre Verle; Philippe Maurine; Nadine Azémard; Daniel Auvergne (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, 2004)

Temperature Dependence in Low Power CMOS UDSM Process - B. Lasbouygues; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, 2004)

Design Optimization with Automated Cell Generation - A. Landrault; Nadine Azémard; Philippe Maurine; Michel Robert; Daniel Auvergne (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, 2004)

Physical Extension of the Logical Effort Model - B. Lasbouygues; Robin Wilson; Philippe Maurine; Nadine Azémard; Daniel Auvergne (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, 2004)

Design Techniques for EEPROMs Embedded in Portable Systems on Chips - Jean Michel Daga; Caroline Papaix; Marc Merandat; Stephane Ricard; Giuseppe Medulla; Jeanine Guichaoua; Daniel Auvergne (IEEE Des. Test Comput., 2003)

Continuous representation of the performance of a CMOS library - B. Lasbouygues; Joel Schindler; Sylvain Engels; Philippe Maurine; Nadine Azémard; Daniel Auvergne (ESSCIRC 2003 - 29th European Solid-State Circuits Conference, Estoril, Portugal, September 16-18, 2003, 2003)

CMOS Gate Sizing under Delay Constraint - Alexandre Verle; Xavier Michel; Philippe Maurine; Nadine Azémard; Daniel Auvergne (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, 2003)

Metric Definition for Circuit Speed Optimization - Xavier Michel; Alexandre Verle; Nadine Azémard; Philippe Maurine; Daniel Auvergne (Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings, 2003)

Transition time modeling in deep submicron CMOS - Philippe Maurine; Mustapha Rezzoug; Nadine Azémard; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Gate speed improvement at minimal power dissipation - Philippe Maurine; Xavier Michel; Nadine Azémard; Daniel Auvergne (IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, 2002)

Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications - Wenceslas Rahajandraibe; Christian Dufaza; Daniel Auvergne; Bruno Cialdella; Bernard Majoux; Vivek Chowdhury (2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, 2002)

Crosstalk Measurement Technique for CMOS ICs - Fabrice Picot; Philippe Coll; Daniel Auvergne (Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, 2002)

Transistor Level Synthesis Dedicated to Fast I.P. Prototyping - Alexis Landrault; Ludovic Pellier; Alexandre Richard; Christian Jay; Michel Robert; Daniel Auvergne (Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, 2002)

Structure Independent Representation of Output Transition Time for CMOS Library - Philippe Maurine; Nadine Azémard; Daniel Auvergne (Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, 2002)

POPS: A tool for delay/power performance optimization - Nadine Azémard; Daniel Auvergne (J. Syst. Archit., 2001)

Gate Sizing for Low Power Design - Philippe Maurine; Nadine Azémard; Daniel Auvergne (SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France, 2001)

Feasible Delay Bound Definition - Nadine Azémard; M. Aline; Philippe Maurine; Daniel Auvergne (SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France, 2001)

Output transition time modeling of CMOS structures - Philippe Maurine; Mustapha Rezzoug; Daniel Auvergne (Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, 2001)

Delay bound determination for timing closure satisfaction - Nadine Azémard; M. Aline; Daniel Auvergne (Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, 2001)

Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions - Jean Michel Daga; Caroline Papaix; Marc Merandat; Stephane Ricard; Giuseppe Medulla; Jeanine Guichaoua; Daniel Auvergne (8th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2000), 7-8 August 2000, San Jose, CA, USA, 2000)

Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design - Philippe Maurine; Mustapha Rezzoug; Daniel Auvergne (Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, 2000)

Second Generation Delay Model for Submicron CMOS Process - Mustapha Rezzoug; Philippe Maurine; Daniel Auvergne (Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings, 2000)

A comprehensive delay macro modeling for submicrometer CMOS logics - Jean Michel Daga; Daniel Auvergne (IEEE J. Solid State Circuits, 1999)

Delay-power performance analysis - S. Cremoux; M. Aline; Nadine Azémard; Daniel Auvergne (6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999, 1999)

RF Interface Design Using Mixed-Mode Methodology - Augusto Gallegos; Philippe Silvestre; Michel Robert; Daniel Auvergne (VLSI: Systems on a Chip, IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99), December 1-4, 1999, Lisbon, Portugal, 1999)

A Virtual CMOS Library Approach for East Layout Synthesis - Fernando Moraes; Michel Robert; Daniel Auvergne (VLSI: Systems on a Chip, IFIP TC10/WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99), December 1-4, 1999, Lisbon, Portugal, 1999)

A novel macromodel for power estimation in CMOS structures - S. Turgis; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Temperature Effect on Delay for Low Voltage Applications - Jean Michel Daga; E. Ottaviano; Daniel Auvergne (1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, 1998)

Internal power modelling and minimization in CMOS inverters - S. Turgis; Jean Michel Daga; Josep M. Portal; Daniel Auvergne (European Design and Test Conference, ED&TC '97, Paris, France, 17-20 March 1997, 1997)

Delay propagation effect in transistor gates - Denis Deschacht; Christophe Dabrin; Daniel Auvergne (IEEE J. Solid State Circuits, 1996)

Design and selection of buffers for minimum power-delay product - S. Turgis; Nadine Azémard; Daniel Auvergne (1996 European Design and Test Conference, ED&TC 1996, Paris, France, March 11-14, 1996, 1996)

Delay modelling improvement for low voltage applications - Jean Michel Daga; Michel Robert; Daniel Auvergne (Proceedings EURO-DAC'95, European Design Automation Conference with EURO-VHDL, Brighton, England, UK, September 18-22, 1995, 1995)

Explicit evaluation of short circuit power dissipation for CMOS logic structures - S. Turgis; Nadine Azémard; Daniel Auvergne (Proceedings of the 1995 International Symposium on Low Power Design 1995, Dana Point, California, USA, April 23-26, 1995, 1995)

Influence of Locig Block Layout Architecture on FPGA Performance - Michel Robert; Lionel Torres; Fernando Moraes; Daniel Auvergne (Field-Programmable Logic, Architectures, Synthesis and Applications, 4th International Workshop on Field-Programmable Logic and Applications, FPL '94, Prague, Czech Republic, September 7-9, 1994, Proceedings, 1994)

Post-layout timing simulation of CMOS circuits - Denis Deschacht; Michel Robert; Nadine Azémard-Crestani; Daniel Auvergne (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

P.SIZE: a sizing aid for optimized designs - Nadine Azémard; V. Bonzom; Daniel Auvergne (Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992, 1992)

TVA: A timing verifier with analytic temporal modelling - D. Navarro; A. Roy; Michel Robert; Denis Deschacht; Daniel Auvergne (Microprocessing and Microprogramming, 1991)

Synchronous-mode evaluation of delays in CMOS structures - Denis Deschacht; Michel Robert; Daniel Auvergne (IEEE J. Solid State Circuits, 1991)

Formal sizing rules of CMOS circuits - Daniel Auvergne; Nadine Azémard; V. Bonzom; Denis Deschacht; Michel Robert (Proceedings of the conference on European design automation, EURO-DAC'91, Amsterdam, The Netherlands, 1991, 1991)

Input waveform slope effects in CMOS delays - Daniel Auvergne; Nadine Azémard; Denis Deschacht; Michel Robert (IEEE J. Solid State Circuits, 1990)

Path runner: an accurate and fast timing analyser - Denis Deschacht; P. Pinede; Michel Robert; Daniel Auvergne (European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, 1990)

FSPICE: a tool for fault modelling in MOS circuits - Michel Renovell; Gaston Cambon; Daniel Auvergne (Integr., 1985)