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ORCIDB. Venkataramani
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2023
[j27]R. Thilagavathy
, B. Venkataramani:
A Novel Feature Enhancement Technique for ECG Arrhythmia Classification Using Discrete Anamorphic Stretch Transform. Circuits Syst. Signal Process. 42(1): 277-306 (2023)- 2022
- [j26]Thilagavathy R, Venkataramani B:
A novel ECG signal compression using wavelet and discrete anamorphic stretch transforms. Biomed. Signal Process. Control. 71(Part): 102773 (2022) - 2021
- [j25]R. Sanjay, B. Venkataramani, S. Kumaravel, V. Senthil Rajan, K. Hari Kishore:
A Low-Noise Area-Efficient Current Feedback Instrumentation Amplifier. Circuits Syst. Signal Process. 40(3): 1496-1510 (2021) - 2020
- [j24]K. Hari Kishore, Prakash Sat, B. Kasi Raju, Venkataramani B:
Highly linear inductorless asymmetric capacitive cross-coupled wideband balun-LNAs. Comput. Electr. Eng. 83: 106614 (2020) - [j23]R. K. Kavitha, A. Khajamastan, Y. Rama Akhilesh, B. Venkataramani:
High-performance asynchronous pipeline using embedded delay element. Microprocess. Microsystems 73: 102955 (2020) - [j22]V. Senthil Rajan, K. Hari Kishore, R. Sanjay, S. Kumaravel, B. Venkataramani:
A novel programmable attenuator based low Gm-OTA for biomedical applications. Microelectron. J. 97: 104721 (2020)
2010 – 2019
- 2019
- [j21]K. Hari Kishore, B. Venkataramani, B. Kasi Raju:
Wideband Balun-LNAs using asymmetric CCC technique for WLAN and mobile WiMAX applications. Microelectron. J. 90: 105-116 (2019) - [j20]K. Hari Kishore, V. Senthil Rajan, R. Sanjay, B. Venkataramani:
Reconfigurable low voltage low power dual-band self-cascode current-reuse quasi-differential LNA for 5G. Microelectron. J. 92 (2019) - 2017
- [j19]R. K. Kavitha, Vineeth Johns Toms, Vipin Vinayakan, B. Venkataramani:
Low Power Data Driven Conditional Precharge Dynamic Flip Flop. J. Low Power Electron. 13(4): 569-575 (2017) - [j18]R. Raja, B. Venkataramani, K. Hari Kishore:
A 1-V 2.4 GHz Low-Power CMOS LNA Using Gain-Boosting and Derivative Superposition Techniques for WSN. Wirel. Pers. Commun. 96(1): 383-402 (2017) - [j17]R. Raja, B. Venkataramani, K. Hari Kishore:
Erratum to: A 1-V 2.4 GHz Low-Power CMOS LNA Using Gain-Boosting and Derivative Superposition Techniques for WSN. Wirel. Pers. Commun. 96(1): 403 (2017) - [c18]Greeshma R, Anoop V. K, B. Venkataramani:
A Novel Opamp and Capacitor Sharing 10 Bit 20 MS/s Low Power Pipelined ADC in 0.18µm CMOS Technology. ISVLSI 2017: 594-599 - [c17]Thilagavathy R, Susmitha Settivari, Venkataramani B, Bhaskar Manickam:
FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT. VDAT 2017: 75-80 - 2016
- [j16]R. Raja, Ramesh Theegala, B. Venkataramani:
A Low-Power and Highly Linear Merged Low Noise Amplifier-Mixer for Wireless Sensor Network Applications. J. Low Power Electron. 12(4): 368-384 (2016) - [j15]S. Kumaravel, Anand Kukde, B. Venkataramani, R. Raja:
A high linearity and high gain Folded Cascode LNA for narrowband receiver applications. Microelectron. J. 54: 101-108 (2016) - 2015
- [c16]D. Malathi, R. Greeshma, R. Sanjay, B. Venkataramani:
A 4 bit medium speed flash ADC using inverter based comparator in 0.18μm CMOS. VDAT 2015: 1-5 - 2014
- [j14]M. Bhaskar, B. Venkataramani:
Differential Voltage Mode On-Chip Serial Transceiver for Global Interconnects. J. Low Power Electron. 10(2): 247-258 (2014) - 2013
- [j13]S. Kumaravel, K. N. Bharadwaj Tirumala, B. Venkataramani, R. Raja:
A Power Efficient Low Noise Preamplifier for Biomedical Applications. J. Low Power Electron. 9(4): 501-509 (2013) - [j12]M. Bhaskar, A. Jaswanth, B. Venkataramani:
Design of a novel differential on-chip wave-pipelined serial interconnect with surfing. Microprocess. Microsystems 37(6-7): 649-660 (2013) - [j11]J. Manikandan, B. Venkataramani:
System-on-programmable-chip implementation of diminishing learning based pattern recognition system. Int. J. Mach. Learn. Cybern. 4(4): 347-363 (2013) - [c15]J. Manikandan, V. K. Agrawal, B. Venkataramani:
Design of a Biometric Security System Using Support Vector Machine Classifier. ICACNI 2013: 173-181 - [c14]R. Raja, S. Kumaravel, B. Venkataramani, Ganesh Yashavant Magar:
A 1.8V 2.4 GHz Folded-Switch Mixer for Direct Conversion Receiver. ISED 2013: 1-5 - 2012
- [c13]S. Kumaravel, B. Venkataramani, S. Rishi, V. Sri Vijay, B. Shailendra:
An enhanced folded cascode OTA with push pull input stage. SSD 2012: 1-6 - 2011
- [j10]J. Manikandan, B. Venkataramani:
Design of a real time automatic speech recognition system using Modified One Against All SVM classifier. Microprocess. Microsystems 35(6): 568-578 (2011) - [j9]S. Ramasamy, B. Venkataramani:
A Low Power Reconfigurable Analog Baseband Block for Software Defined Radio. J. Signal Process. Syst. 62(2): 131-144 (2011) - [c12]J. Manikandan, B. Venkataramani, K. Girish, H. Karthic, V. Siddharth:
Hardware Implementation of Real-Time Speech Recognition System Using TMS320C6713 DSP. VLSI Design 2011: 250-255 - 2010
- [j8]J. Manikandan, B. Venkataramani:
Study and evaluation of a multi-class SVM classifier using diminishing learning technique. Neurocomputing 73(10-12): 1676-1685 (2010) - [c11]J. Manikandan, B. Venkataramani, M. Bhaskar, K. Ashish, R. Raghul, V. Mathangi:
Implementation of a Novel Phoneme Recognition System Using TMS320C6713 DSP. VLSI Design 2010: 27-32
2000 – 2009
- 2009
- [j7]S. Ramasamy, B. Venkataramani, P. Meenatchisundaram:
A low power CMOS voltage reference circuit with sub threshold MOSFETs. Int. J. Inf. Commun. Technol. 2(1/2): 94-107 (2009) - [j6]V. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar:
Software/Hardware Co-design of HMM Based Speaker Independent Isolated Digit Recognition System. J. Comput. 4(2): 154-159 (2009) - [j5]G. Seetharaman, B. Venkataramani:
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits. ACM Trans. Reconfigurable Technol. Syst. 2(2): 11:1-11:19 (2009) - [c10]B. Malarkodi, P. Rakesh, B. Venkataramani:
Performance Evaluation of On-Demand Multipath Distance Vector Routing Protocol under Different Traffic Models. ARTCom 2009: 77-80 - [c9]B. Malarkodi, P. Gopal, B. Venkataramani:
Performance Evaluation of Adhoc Networks with Different Multicast Routing Protocols and Mobility Models. ARTCom 2009: 81-84 - [c8]B. Malarkodi, B. Prasana, B. Venkataramani:
A Scheduling Policy for Battery Management in Mobile Devices. NetCoM 2009: 83-87 - [c7]J. Manikandan, B. Venkataramani:
Design of a Modified One-Against-All SVM Classifier. SMC 2009: 1869-1874 - [c6]S. Ramasamy, B. Venkataramani, R. Niranjini, K. Suganya:
100KHz-20MHz Programmable Subthreshold Gm-C Low-Pass Filter in 0.18µ-m CMOS. VLSI Design 2009: 105-110 - [c5]J. Manikandan, B. Venkataramani, V. Avanthi:
FPGA Implementation of Support Vector Machine Based Isolated Digit Recognition System. VLSI Design 2009: 347-352 - [c4]V. Vireen, N. Venugopalachary, G. Seetharaman, B. Venkataramani:
Built in Self Test Based Design of Wave-Pipelined Circuits in ASICs. VLSI Design 2009: 473-478 - 2008
- [j4]G. Seetharaman, B. Venkataramani, Gopalakrishnan Lakshminarayanan:
Automation techniques for implementation of hybrid wave-pipelined 2D DWT. J. Real Time Image Process. 3(3): 217-229 (2008) - [j3]Gopalakrishnan Seetharaman, Balasubramanian Venkataramani, Gopalakrishnan Lakshminarayanan:
VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme. VLSI Design 2008: 512746:1-512746:8 (2008) - [c3]S. Ramasamy, B. Venkataramani, K. Anbugeetha:
VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair. VLSI Design 2008: 317-322 - 2007
- [c2]Gopalakrishnan Seetharaman, Balasubramanian Venkataramani:
SOC implementation of wave-pipelined circuits. FPT 2007: 9-16 - [c1]V. Amudha, B. Venkataramani, R. Vinoth Kumar, S. Ravishankar:
SOC Implementation of HMM Based Speaker Independent Isolated Digit Recognition System. VLSI Design 2007: 848-853 - 2005
- [j2]Gopalakrishnan Lakshminarayanan, B. Venkataramani:
Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks. IEEE Trans. Very Large Scale Integr. Syst. 13(7): 783-793 (2005)
1990 – 1999
- 1997
- [j1]B. Venkataramani, Sanjay K. Bose, K. R. Srivathsan:
Queuing analysis of a non-pre-emptive MMPP/D/1 priority system. Comput. Commun. 20(11): 999-1018 (1997)
Coauthor Index
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