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ORCIDPaul M. Rosinger
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2010 – 2019
- 2010
[j8]Alireza Ejlali
, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi, Luca Benini:
Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 1-14 (2010)
2000 – 2009
- 2008
- [j7]Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi:
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. J. Electron. Test. 24(1-3): 247-257 (2008) - [j6]S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosinger, Bashir M. Al-Hashimi, Peter Harrod:
Bridging Fault Test Method With Adaptive Power Management Awareness. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1117-1127 (2008) - [c14]Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi:
MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC. DDECS 2008: 98-103 - [c13]S. Saqib Khursheed, Paul M. Rosinger, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod:
Bridge Defect Diagnosis for Multiple-Voltage Design. ETS 2008: 99-104 - [c12]Rishad A. Shafik, Paul M. Rosinger, Bashir M. Al-Hashimi:
SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation. IOLTS 2008: 99-104 - 2007
- [c11]Urban Ingelsson, Paul M. Rosinger, S. Saqib Khursheed, Bashir M. Al-Hashimi, Peter Harrod:
Resistive Bridging Faults DFT with Adaptive Power Management Awareness. ATS 2007: 101-106 - [c10]Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosinger, Seyed Ghassem Miremadi:
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks. DATE 2007: 1647-1652 - [i1]Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty:
Rapid Generation of Thermal-Safe Test Schedules. CoRR abs/0710.4797 (2007) - 2006
- [j5]Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard:
Reducing Power Dissipation in SRAM during Test. J. Low Power Electron. 2(2): 271-280 (2006) - [j4]Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty:
Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2502-2512 (2006) - [j3]Alireza Ejlali, Bashir M. Al-Hashimi, Marcus T. Schmitz, Paul M. Rosinger, Seyed Ghassem Miremadi:
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 323-335 (2006) - [c9]Luigi Dilillo, Paul M. Rosinger, Bashir M. Al-Hashimi, Patrick Girard:
Minimizing test power in SRAM through reduction of pre-charge activity. DATE 2006: 1159-1164 - [c8]Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi:
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. DFT 2006: 477-485 - 2005
- [c7]Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty:
Rapid Generation of Thermal-Safe Test Schedules. DATE 2005: 840-845 - [c6]Enkelejda Tafaj, Paul M. Rosinger, Bashir M. Al-Hashimi, Krishnendu Chakrabarty:
Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling. DFT 2005: 544-551 - [c5]Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger:
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy. ISLPED 2005: 281-286 - 2004
- [j2]Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1142-1153 (2004) - [c4]Matheos Lampropoulos, Bashir M. Al-Hashimi, Paul M. Rosinger:
Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique. DATE 2004: 1372-1373 - 2002
- [j1]Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Power profile manipulation: a new approach for reducing test application time under power constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1217-1225 (2002) - [c3]Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Scan Architecture for Shift and Capture Cycle Power Reduction. DFT 2002: 129-137 - [c2]Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding. ICCD 2002: 474-479 - 2001
- [c1]Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici:
Power constrained test scheduling using power profile manipulation. ISCAS (5) 2001: 251-254
Coauthor Index
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