Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs - Lun Ye; Foong-Charn Chang; Peter Feldmann; Rakesh Chadha; Nagaraj Ns; Frank Cano (1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, 1999)

An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits - Foong-Charn Chang; Chin-Fu Chen; Prasad Subramaniam (Proceedings of the 25th ACM/IEEE Conference on Design Automation, DAC '88, Anaheim, CA, USA, June 12-15, 1988, 1988)